Lines Matching refs:v16
237 smull v16.4s, v10.4h, v0.4h[0]
238 smlal v16.4s, v11.4h, v2.4h[2]
272 smlal v16.4s, v12.4h, v5.4h[0]
273 smlal v16.4s, v13.4h, v7.4h[2]
307 smlsl v16.4s, v10.4h, v6.4h[0]
308 smlsl v16.4s, v11.4h, v3.4h[2]
346 smlsl v16.4s, v12.4h, v1.4h[0]
347 smlsl v16.4s, v13.4h, v1.4h[2]
383 smlsl v16.4s, v10.4h, v0.4h[0]
384 smlsl v16.4s, v11.4h, v6.4h[2]
415 smlal v16.4s, v12.4h, v7.4h[0]
416 smlal v16.4s, v13.4h, v4.4h[2]
453 smlal v16.4s, v10.4h, v2.4h[0]
454 smlal v16.4s, v11.4h, v0.4h[2]
481 smlal v16.4s, v12.4h, v3.4h[0]
482 smlal v16.4s, v13.4h, v5.4h[2]
495 add v14.4s, v16.4s , v28.4s
496 sub v26.4s, v16.4s , v28.4s
499 add v16.4s, v18.4s , v30.4s
509 sqrshrn v13.4h, v16.4s,#shift_stage1_idct //// x3 = (a3 + b3 + rnd) >> 7(shift_stage1_idct)
598 smull v16.4s, v10.4h, v0.4h[0]
599 v16.4s, v11.4h, v6.4h[2]
628 smlsl v16.4s, v12.4h, v3.4h[0]
629 smlsl v16.4s, v13.4h, v3.4h[2]
669 smlal v16.4s, v10.4h, v6.4h[0]
670 smlal v16.4s, v11.4h, v0.4h[2]
704 smlal v16.4s, v12.4h, v7.4h[0]
705 smlsl v16.4s, v13.4h, v2.4h[2]
746 smlsl v16.4s, v10.4h, v0.4h[0]
747 smlal v16.4s, v11.4h, v5.4h[2]
776 smlal v16.4s, v12.4h, v1.4h[0]
777 smlal v16.4s, v13.4h, v7.4h[2]
810 smlsl v16.4s, v10.4h, v2.4h[0]
811 smlsl v16.4s, v11.4h, v4.4h[2]
842 smlal v16.4s, v12.4h, v5.4h[0]
843 smlal v16.4s, v13.4h, v1.4h[2]
854 add v14.4s, v16.4s , v28.4s
855 sub v26.4s, v16.4s , v28.4s
858 add v16.4s, v18.4s , v30.4s
868 sqrshrn v13.4h, v16.4s,#shift_stage1_idct //// x3 = (a3 + b3 + rnd) >> 7(shift_stage1_idct)
938 smull v16.4s, v10.4h, v0.4h[0]
939 smlsl v16.4s, v11.4h, v5.4h[2]
971 smlsl v16.4s, v12.4h, v5.4h[0]
972 smlal v16.4s, v13.4h, v0.4h[2]
1005 smlsl v16.4s, v10.4h, v6.4h[0]
1006 smlsl v16.4s, v11.4h, v4.4h[2]
1041 smlal v16.4s, v12.4h, v1.4h[0]
1042 smlsl v16.4s, v13.4h, v6.4h[2]
1078 smlsl v16.4s, v10.4h, v0.4h[0]
1079 smlal v16.4s, v11.4h, v1.4h[2]
1108 smlsl v16.4s, v12.4h, v7.4h[0]
1109 smlsl v16.4s, v13.4h, v3.4h[2]
1144 smlal v16.4s, v10.4h, v2.4h[0]
1145 smlsl v16.4s, v11.4h, v7.4h[2]
1172 smlsl v16.4s, v12.4h, v3.4h[0]
1173 smlal v16.4s, v13.4h, v2.4h[2]
1184 add v14.4s, v16.4s , v28.4s
1185 sub v26.4s, v16.4s , v28.4s
1188 add v16.4s, v18.4s , v30.4s
1198 sqrshrn v13.4h, v16.4s,#shift_stage1_idct //// x3 = (a3 + b3 + rnd) >> 7(shift_stage1_idct)
1268 smull v16.4s, v10.4h, v0.4h[0]
1269 smlsl v16.4s, v11.4h, v1.4h[2]
1303 smlal v16.4s, v12.4h, v3.4h[0]
1304 smlsl v16.4s, v13.4h, v4.4h[2]
1339 smlal v16.4s, v10.4h, v6.4h[0]
1340 smlsl v16.4s, v11.4h, v7.4h[2]
1375 smlsl v16.4s, v12.4h, v7.4h[0]
1376 smlal v16.4s, v13.4h, v5.4h[2]
1411 smlsl v16.4s, v10.4h, v0.4h[0]
1412 smlal v16.4s, v11.4h, v2.4h[2]
1446 smlsl v16.4s, v12.4h, v1.4h[0]
1447 smlal v16.4s, v13.4h, v0.4h[2]
1482 smlsl v16.4s, v10.4h, v2.4h[0]
1483 smlal v16.4s, v11.4h, v3.4h[2]
1513 smlsl v16.4s, v12.4h, v5.4h[0]
1514 smlal v16.4s, v13.4h, v6.4h[2]
1525 add v14.4s, v16.4s , v28.4s
1526 sub v26.4s, v16.4s , v28.4s
1529 add v16.4s, v18.4s , v30.4s
1539 sqrshrn v13.4h, v16.4s,#shift_stage1_idct //// x3 = (a3 + b3 + rnd) >> 7(shift_stage1_idct)
1640 smull v16.4s, v10.4h, v0.4h[0]
1641 smlal v16.4s, v11.4h, v2.4h[2]
1672 smlal v16.4s, v12.4h, v5.4h[0]
1673 smlal v16.4s, v13.4h, v7.4h[2]
1703 smlsl v16.4s, v10.4h, v6.4h[0]
1704 smlsl v16
1736 smlsl v16.4s, v12.4h, v1.4h[0]
1737 smlsl v16.4s, v13.4h, v1.4h[2]
1770 smlsl v16.4s, v10.4h, v0.4h[0]
1771 smlsl v16.4s, v11.4h, v6.4h[2]
1799 smlal v16.4s, v12.4h, v7.4h[0]
1800 smlal v16.4s, v13.4h, v4.4h[2]
1832 smlal v16.4s, v10.4h, v2.4h[0]
1833 smlal v16.4s, v11.4h, v0.4h[2]
1857 smlal v16.4s, v12.4h, v3.4h[0]
1858 smlal v16.4s, v13.4h, v5.4h[2]
1869 add v14.4s, v16.4s , v28.4s
1870 sub v26.4s, v16.4s , v28.4s
1873 add v16.4s, v18.4s , v30.4s
1883 sqrshrn v13.4h, v16.4s,#shift_stage2_idct //// x3 = (a3 + b3 + rnd) >> 7(shift_stage2_idct)
1954 smull v16.4s, v10.4h, v0.4h[0]
1955 smlal v16.4s, v11.4h, v6.4h[2]
1983 smlsl v16.4s, v12.4h, v3.4h[0]
1984 smlsl v16.4s, v13.4h, v3.4h[2]
2019 smlal v16.4s, v10.4h, v6.4h[0]
2020 smlal v16.4s, v11.4h, v0.4h[2]
2053 smlal v16.4s, v12.4h, v7.4h[0]
2054 smlsl v16.4s, v13.4h, v2.4h[2]
2088 smlsl v16.4s, v10.4h, v0.4h[0]
2089 smlal v16.4s, v11.4h, v5.4h[2]
2116 smlal v16.4s, v12.4h, v1.4h[0]
2117 smlal v16.4s, v13.4h, v7.4h[2]
2147 smlsl v16.4s, v10.4h, v2.4h[0]
2148 smlsl v16.4s, v11.4h, v4.4h[2]
2175 smlal v16.4s, v12.4h, v5.4h[0]
2176 smlal v16.4s, v13.4h, v1.4h[2]
2187 add v14.4s, v16.4s , v28.4s
2188 sub v26.4s, v16.4s , v28.4s
2191 add v16.4s, v18.4s , v30.4s
2201 sqrshrn v13.4h, v16.4s,#shift_stage2_idct //// x3 = (a3 + b3 + rnd) >> 7(shift_stage2_idct)
2269 smull v16.4s, v10.4h, v0.4h[0]
2270 smlsl v16.4s, v11.4h, v5.4h[2]
2297 smlsl v16.4s, v12.4h, v5.4h[0]
2298 smlal v16.4s, v13.4h, v0.4h[2]
2331 smlsl v16.4s, v10.4h, v6.4h[0]
2332 smlsl v16.4s, v11.4h, v4.4h[2]
2363 smlal v16.4s, v12.4h, v1.4h[0]
2364 smlsl v16.4s, v13.4h, v6.4h[2]
2397 smlsl v16.4s, v10.4h, v0.4h[0]
2398 smlal v16.4s, v11.4h, v1.4h[2]
2425 smlsl v16.4s, v12.4h, v7.4h[0]
2426 smlsl v16.4s, v13.4h, v3.4h[2]
2456 smlal v16.4s, v10.4h, v2.4h[0]
2457 smlsl v16.4s, v11.4h, v7.4h[2]
2483 smlsl v16.4s, v12.4h, v3.4h[0]
2484 smlal v16.4s, v13.4h, v2.4h[2]
2495 add v14.4s, v16.4s , v28.4s
2496 sub v26.4s, v16.4s , v28.4s
2499 add v16.4s, v18.4s , v30.4s
2509 sqrshrn v13.4h, v16.4s,#shift_stage2_idct //// x3 = (a3 + b3 + rnd) >> 7(shift_stage2_idct)
2579 smull v16.4s, v10.4h, v0.4h[0]
2580 smlsl v16.4s, v11.4h, v1.4h[2]
2611 smlal v16.4s, v12.4h, v3.4h[0]
2612 smlsl v16.4s, v13.4h, v4.4h[2]
2645 smlal v16.4s, v10.4h, v6.4h[0]
2646 smlsl v16.4s, v11.4h, v7.4h[2]
2679 smlsl v16.4s, v12.4h, v7.4h[0]
2680 smlal v16.4s, v13.4h, v5.4h[2]
2713 smlsl v16.4s, v10.4h, v0.4h[0]
2714 smlal v16.4s, v11.4h, v2.4h[2]
2741 smlsl v16.4s, v12.4h, v1.4h[0]
2742 smlal v16.4s, v13.4h, v0.4h[2]
2774 smlsl v16.4s, v10.4h, v2.4h[0]
2775 smlal v16.4s, v11.4h, v3.4h[2]
2802 smlsl v16.4s, v12.4h, v5.4h[0]
2803 smlal v16.4s, v13.4h, v6.4h[2]
2814 add v14.4s, v16.4s , v28.4s
2815 sub v26.4s, v16.4s , v28.4s
2818 add v16.4s, v18.4s , v30.4s
2828 sqrshrn v13.4h, v16.4s,#shift_stage2_idct //// x3 = (a3 + b3 + rnd) >> 7(shift_stage2_idct)
2880 ld1 {v16.8h},[x0],#16
2917 // swapping v12 upper and v16 lower 64bits
2919 mov v12.d[1], v16.d[0]
2920 mov v16.d[0], v13.d[0]
2945 uaddw v16.8h, v16.8h , v28.8b
2955 sqxtun v14.8b, v16.8h
2975 ld1 {v16.8h},[x0],#16
2992 // swapping v12 upper and v16 lower 64bits
2994 mov v12.d[1], v16.d[0]
2995 mov v16.d[0], v13.d[0]
3020 uaddw v16.8h, v16.8h , v28.8b
3030 sqxtun v14.8b, v16.8h
