Lines Matching refs:Address
15 #include "lldb/Core/Address.h"
231 // Write "bits (32) UNKNOWN" to memory address "address". Helper function for many ARM instructions.
233 EmulateInstructionARM::WriteBits32UnknownToMemory (addr_t address)
242 if (!MemAWrite (context, address, random_data, addr_byte_size))
326 // consecutive memory locations ending just below the address in SP, and updates
337 address = SP - 4*BitCount(registers);
344 MemA[address,4] = bits(32) UNKNOWN;
346 MemA[address,4] = R[i];
347 address = address + 4;
352 MemA[address,4] = PCStoreValue();
456 // consecutive memory locations staring at the address in SP, and updates
466 address = SP;
469 R[i] = if UnalignedAllowed then MemU[address,4] else MemA[address,4]; address = address + 4;
472 LoadWritePC(MemU[address,4]);
474 LoadWritePC(MemA[address,4]);
1190 address = if add then (base + imm32) else (base - imm32);
1191 data = MemU[address,4];
1193 if address<1:0> == '00' then LoadWritePC(data); else UNPREDICTABLE;
1194 elsif UnalignedSupport() || address<1:0> = '00' then
1198 R[t] = ROR(data, 8*UInt(address<1:0>));
1221 addr_t base; // the base address
1222 addr_t address; // the PC relative address
1243 address = base + imm32;
1245 address = base - imm32;
1247 context.SetRegisterPlusOffset(pc_reg, address - base);
1248 data = MemURead(context, address, 4, 0, &success);
1254 if (Bits32(address, 1, 0) == 0)
1263 else if (UnalignedSupport() || Bits32(address, 1, 0) == 0)
1420 // at a PC-relative address, and changes instruction set from ARM to Thumb, or
1453 addr_t lr; // next instruction address
1454 addr_t target; // target address
1459 lr = pc | 1u; // return address
1477 lr = pc | 1u; // return address
1494 lr = pc - 4; // return address
1500 lr = pc - 4; // return address
1516 // Branch with Link and Exchange (register) calls a subroutine at an address and
1545 addr_t lr; // next instruction address
1548 uint32_t Rm; // the register with the target address
1551 lr = (pc - 2) | 1u; // return address
1560 lr = pc - 4; // return address
1583 // Branch and Exchange causes a branch to an address and instruction set specified by a register.
1600 uint32_t Rm; // the register with the target address
1628 // address and instruction set specified by a register as though it were a BX instruction.
1654 uint32_t Rm; // the register with the target address
1890 address = if index then offset_addr else R[n];
1891 MemU[address,4] = if t == 15 then PCStoreValue() else R[t];
1992 address = SP - imm32;
1996 MemA[address,4] = S[d+r]; address = address+4;
2000 MemA[address,4] = if BigEndian() then D[d+r]<63:32> else D[d+r]<31:0>;
2001 MemA[address+4,4] = if BigEndian() then D[d+r]<31:0> else D[d+r]<63:32>;
2002 address = address+8;
2089 address = SP;
2093 S[d+r] = MemA[address,4]; address = address+4;
2096 word1 = MemA[address,4]; word2 = MemA[address+4,4]; address = address+8;
2193 addr_t lr; // next instruction address
2200 lr = (pc + 2) | 1u; // return address
2205 lr = pc + 4; // return address
2243 // Branch causes a branch to a target address.
2265 addr_t target; // target address
2348 addr_t target; // target address
2391 uint32_t Rn; // the base register which contains the address of the table of branch lengths
2408 // Read the address of the table from the operand register Rn.
2419 // the offsetted table address
2433 // target address
3338 // address from a base register. Optionally the address just above the highest of those locations
3347 address = R[n];
3351 R[i] = MemA[address, 4]; address = address + 4;
3353 LoadWritePC (MemA[address, 4]);
3441 // R[i] = MemA [address, 4]; address = address + 4;
3455 //LoadWritePC (MemA [address, 4]);
3483 // LDMDA loads multiple registers from consecutive memory locations using an address from a base register.
3484 // The consecutive memory locations end at this address and the address just below the lowest of those locations
3493 address = R[n] - 4*BitCount(registers) + 4;
3497 R[i] = MemA[address,4]; address = address + 4;
3500 LoadWritePC(MemA[address,4]);
3533 // address = R[n] - 4*BitCount(registers) + 4;
3541 addr_t address = Rn - (addr_byte_size * BitCount (registers)) + addr_byte_size;
3555 // R[i] = MemA[address,4]; address = address + 4;
3556 context.SetRegisterPlusOffset (dwarf_reg, Rn - (address + offset));
3557 uint32_t data = MemARead (context, address + offset, addr_byte_size, 0, &success);
3567 // LoadWritePC(MemA[address,4]);
3571 uint32_t data = MemARead (context, address + offset, addr_byte_size, 0, &success);
3600 // LDMDB loads multiple registers from consecutive memory locations using an address from a base register. The
3601 // consecutive memory lcoations end just below this address, and the address of the lowest of those locations can
3610 address = R[n] - 4*BitCount(registers);
3614 R[i] = MemA[address,4]; address = address + 4;
3616 LoadWritePC(MemA[address,4]);
3671 // address = R[n] - 4*BitCount(registers);
3679 addr_t address = Rn - (addr_byte_size * BitCount (registers));
3684 context.SetRegisterPlusOffset (dwarf_reg, Rn - address);
3690 // R[i] = MemA[address,4]; address = address + 4;
3691 context.SetRegisterPlusOffset (dwarf_reg, Rn - (address + offset));
3692 uint32_t data = MemARead (context, address + offset, addr_byte_size, 0, &success);
3704 // LoadWritePC(MemA[address,4]);
3708 uint32_t data = MemARead (context, address + offset, addr_byte_size, 0, &success);
3737 // LDMIB loads multiple registers from consecutive memory locations using an address from a base register. The
3738 // consecutive memory locations start just above this address, and thea ddress of the last of those locations can
3746 address = R[n] + 4;
3750 R[i] = MemA[address,4]; address = address + 4;
3752 LoadWritePC(MemA[address,4]);
3782 // address = R[n] + 4;
3790 addr_t address = Rn + addr_byte_size;
3802 // R[i] = MemA[address,4]; address = address + 4;
3805 uint32_t data = MemARead (context, address + offset, addr_byte_size, 0, &success);
3817 // LoadWritePC(MemA[address,4]);
3821 uint32_t data = MemARead (context, address + offset, addr_byte_size, 0, &success);
3850 // Load Register (immediate) calculates an address from a base register value and
3862 address = if index then offset_addr else R[n];
3863 data = MemU[address,4];
3866 if address<1:0> == '00' then LoadWritePC(data); else UNPREDICTABLE;
3867 elsif UnalignedSupport() || address<1:0> = '00' then
3879 uint32_t imm32; // the immediate offset used to form the address
3880 addr_t offset_addr; // the offset address
3881 addr_t address; // the calculated address
3962 address = (index ? offset_addr : base);
3981 // Read memory from the address.
3982 data = MemURead(context, address, 4, 0, &success);
3988 if (Bits32(address, 1, 0) == 0)
3996 else if (UnalignedSupport() || Bits32(address, 1, 0) == 0)
4007 // STM (Store Multiple Increment After) stores multiple registers to consecutive memory locations using an address
4008 // from a base register. The consecutive memory locations start at this address, and teh address just above the last
4016 address = R[n];
4021 MemA[address,4] = bits(32) UNKNOWN; // Only possible for encodings T1 and A1
4023 MemA[address,4] = R[i];
4024 address = address + 4;
4027 MemA[address,4] = PCStoreValue();
4089 // address = R[n];
4091 const addr_t address = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
4111 // MemA[address,4] = bits(32) UNKNOWN; // Only possible for encodings T1 and A1
4112 WriteBits32UnknownToMemory (address + offset);
4115 // MemA[address,4] = R[i];
4123 if (!MemAWrite (context, address + offset, data, addr_byte_size))
4127 // address = address + 4;
4133 // MemA[address,4] = PCStoreValue();
4143 if (!MemAWrite (context, address + offset, pc, addr_byte_size))
4153 addr_t data = address + offset;
4161 // STMDA (Store Multiple Decrement After) stores multiple registers to consecutive memory locations using an address
4162 // from a base register. The consecutive memory locations end at this address, and the address just below the lowest
4170 address = R[n] - 4*BitCount(registers) + 4;
4175 MemA[address,4] = bits(32) UNKNOWN;
4177 MemA[address,4] = R[i];
4178 address = address + 4;
4181 MemA[address,4] = PCStoreValue();
4212 // address = R[n] - 4*BitCount(registers) + 4;
4218 addr_t address = Rn - (addr_byte_size * BitCount (registers)) + 4;
4236 // MemA[address,4] = bits(32) UNKNOWN;
4237 WriteBits32UnknownToMemory (address + offset);
4240 // MemA[address,4] = R[i];
4247 context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, Rn - (address + offset));
4248 if (!MemAWrite (context, address + offset, data, addr_byte_size))
4252 // address = address + 4;
4258 // MemA[address,4] = PCStoreValue();
4268 if (!MemAWrite (context, address + offset, pc, addr_byte_size))
4286 // STMDB (Store Multiple Decrement Before) stores multiple registers to consecutive memory locations using an address
4287 // from a base register. The consecutive memory locations end just below this address, and the address of the first of
4295 address = R[n] - 4*BitCount(registers);
4300 MemA[address,4] = bits(32) UNKNOWN; // Only possible for encoding A1
4302 MemA[address,4] = R[i];
4303 address = address + 4;
4306 MemA[address,4] = PCStoreValue();
4362 // address = R[n] - 4*BitCount(registers);
4369 addr_t address = Rn - (addr_byte_size * BitCount (registers));
4387 // MemA[address,4] = bits(32) UNKNOWN; // Only possible for encoding A1
4388 WriteBits32UnknownToMemory (address + offset);
4391 // MemA[address,4] = R[i];
4398 context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, Rn - (address + offset));
4399 if (!MemAWrite (context, address + offset, data, addr_byte_size))
4403 // address = address + 4;
4409 // MemA[address,4] = PCStoreValue();
4419 if (!MemAWrite (context, address + offset, pc, addr_byte_size))
4437 // STMIB (Store Multiple Increment Before) stores multiple registers to consecutive memory locations using an address
4438 // from a base register. The consecutive memory locations start just above this address, and the address of the last
4446 address = R[n] + 4;
4451 MemA[address,4] = bits(32) UNKNOWN;
4453 MemA[address,4] = R[i];
4454 address = address + 4;
4457 MemA[address,4] = PCStoreValue();
4487 // address = R[n] + 4;
4494 addr_t address = Rn + addr_byte_size;
4512 // MemA[address,4] = bits(32) UNKNOWN;
4513 WriteBits32UnknownToMemory (address + offset);
4517 // MemA[address,4] = R[i];
4525 if (!MemAWrite (context, address + offset, data, addr_byte_size))
4529 // address = address + 4;
4535 // MemA[address,4] = PCStoreValue();
4545 if (!MemAWrite (context, address + offset, pc, addr_byte_size))
4563 // STR (store immediate) calcualtes an address from a base register value and an immediate offset, and stores a word
4572 address = if index then offset_addr else R[n];
4573 if UnalignedSupport() || address<1:0> == '00' then
4574 MemU[address,4] = R[t];
4576 MemU[address,4] = bits(32) UNKNOWN;
4667 addr_t address;
4679 // address = if index then offset_addr else R[n];
4681 address = offset_addr;
4683 address = base_address;
4690 // if UnalignedSupport() || address<1:0> == '00' then
4691 if (UnalignedSupport () || (BitIsClear (address, 1) && BitIsClear (address, 0)))
4693 // MemU[address,4] = R[t];
4700 int32_t offset = address - base_address;
4702 if (!MemUWrite (context, address, data, addr_byte_size))
4707 // MemU[address,4] = bits(32) UNKNOWN;
4708 WriteBits32UnknownToMemory (address);
4723 // STR (Store Register) calculates an address from a base register value and an offset register value, stores a
4733 address = if index then offset_addr else R[n];
4738 if UnalignedSupport() || address<1:0> == '00' || CurrentInstrSet() == InstrSet_ARM then
4739 MemU[address,4] = data;
4741 MemU[address,4] = bits(32) UNKNOWN;
4837 addr_t address;
4859 // address = if index then offset_addr else R[n];
4861 address = offset_addr;
4863 address = base_address;
4880 // if UnalignedSupport() || address<1:0> == '00' || CurrentInstrSet() == InstrSet_ARM then
4882 || (BitIsClear (address, 1) && BitIsClear (address, 0))
4885 // MemU[address,4] = data;
4893 context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, address - base_address);
4894 if (!MemUWrite (context, address, data, addr_byte_size))
4899 // MemU[address,4] = bits(32) UNKNOWN;
4900 WriteBits32UnknownToMemory (address);
4922 address = if index then offset_addr else R[n];
4923 MemU[address,1] = R[t]<7:0>;
4999 addr_t address;
5010 // address = if index then offset_addr else R[n];
5012 address = offset_addr;
5014 address = base_address;
5016 // MemU[address,1] = R[t]<7:0>
5025 context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, address - base_address);
5033 if (!MemUWrite (context, address, data, 1))
5050 // STRH (register) calculates an address from a base register value and an offset register value, and stores a
5060 address = if index then offset_addr else R[n];
5061 if UnalignedSupport() || address<0> == '0' then
5062 MemU[address,2] = R[t]<15:0>;
5064 MemU[address,2] = bits(16) UNKNOWN;
5176 // address = if index then offset_addr else R[n];
5177 addr_t address;
5179 address = offset_addr;
5181 address = Rn;
5190 // if UnalignedSupport() || address<0> == '0' then
5191 if (UnalignedSupport() || BitIsClear (address, 0))
5193 // MemU[address,2] = R[t]<15:0>;
5208 if (!MemUWrite (context, address, Bits32 (Rt, 15, 0), 2))
5213 // MemU[address,2] = bits(16) UNKNOWN;
5386 // This instruction adds an immediate value to the PC value to form a PC-relative address,
5776 // LDR (immediate, ARM) calculates an address from a base register value and an immediate offset, loads a word
5785 address = if index then offset_addr else R[n];
5786 data = MemU[address,4];
5789 if address<1:0> == '00' then LoadWritePC(data); else UNPREDICTABLE;
5790 elsif UnalignedSupport() || address<1:0> = '00' then
5793 R[t] = ROR(data, 8*UInt(address<1:0>));
5835 addr_t address;
5847 // address = if index then offset_addr else R[n];
5849 address = offset_addr;
5851 address = base_address;
5853 // data = MemU[address,4];
5860 context.SetRegisterPlusOffset (base_reg, address - base_address);
5862 uint64_t data = MemURead (context, address, addr_byte_size, 0, &success);
5878 // if address<1:0> == '00' then LoadWritePC(data); else UNPREDICTABLE;
5879 if (BitIsClear (address, 1) && BitIsClear (address, 0))
5883 context.SetRegisterPlusOffset (base_reg, address - base_address);
5889 // elsif UnalignedSupport() || address<1:0> = '00' then
5890 else if (UnalignedSupport() || (BitIsClear (address, 1) && BitIsClear (address, 0)))
5894 context.SetRegisterPlusOffset (base_reg, address - base_address);
5901 // R[t] = ROR(data, 8*UInt(address<1:0>));
5902 data = ROR (data, Bits32 (address, 1, 0), &success);
5915 // LDR (register) calculates an address from a base register value and an offset register value, loads a word
5925 address = if index then offset_addr else R[n];
5926 data = MemU[address,4];
5929 if address<1:0> == '00' then LoadWritePC(data); else UNPREDICTABLE;
5930 elsif UnalignedSupport() || address<1:0> = '00' then
5934 R[t] = ROR(data, 8*UInt(address<1:0>));
6042 addr_t address;
6055 // address = if index then offset_addr else R[n];
6057 address = offset_addr;
6059 address = Rn;
6061 // data = MemU[address,4];
6067 context.SetRegisterPlusOffset (base_reg, address - Rn);
6069 uint64_t data = MemURead (context, address, addr_byte_size, 0, &success);
6085 // if address<1:0> == '00' then LoadWritePC(data); else UNPREDICTABLE;
6086 if (BitIsClear (address, 1) && BitIsClear (address, 0))
6089 context.SetRegisterPlusOffset (base_reg, address - Rn);
6095 // elsif UnalignedSupport() || address<1:0> = '00' then
6096 else if (UnalignedSupport () || (BitIsClear (address, 1) && BitIsClear (address, 0)))
6100 context.SetRegisterPlusOffset (base_reg, address - Rn);
6109 // R[t] = ROR(data, 8*UInt(address<1:0>));
6110 data = ROR (data, Bits32 (address, 1, 0), &success);
6136 address = if index then offset_addr else R[n];
6137 R[t] = ZeroExtend(MemU[address,1], 32);
6219 addr_t address;
6228 // address = if index then offset_addr else R[n];
6230 address = offset_addr;
6232 address = Rn;
6234 // R[t] = ZeroExtend(MemU[address,1], 32);
6242 context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, address - Rn);
6244 uint64_t data = MemURead (context, address, 1, 0, &success);
6263 // LDRB (literal) calculates an address from the PC value and an immediate offset, loads a byte from memory,
6272 address = if add then (base + imm32) else (base - imm32);
6273 R[t] = ZeroExtend(MemU[address,1], 32);
6320 addr_t address;
6321 // address = if add then (base + imm32) else (base - imm32);
6323 address = base + imm32;
6325 address = base - imm32;
6327 // R[t] = ZeroExtend(MemU[address,1], 32);
6330 context.SetImmediate (address - base);
6332 uint64_t data = MemURead (context, address, 1, 0, &success);
6342 // LDRB (register) calculates an address from a base register value and an offset rigister value, loads a byte from
6353 address = if index then offset_addr else R[n];
6354 R[t] = ZeroExtend(MemU[address,1],32);
6445 addr_t address;
6466 // address
6468 address = offset_addr;
6470 address = Rn;
6472 // R[t] = ZeroExtend(MemU[address,1],32);
6478 context.SetRegisterPlusOffset (base_reg, address - Rn);
6480 uint64_t data = MemURead (context, address, 1, 0, &success);
6499 // LDRH (immediate, Thumb) calculates an address from a base register value and an immediate offset, loads a
6509 address = if index then offset_addr else R[n];
6510 data = MemU[address,2];
6512 if UnalignedSupport() || address<0> = '0' then
6597 addr_t address;
6604 // address = if index then offset_addr else R[n];
6606 address = offset_addr;
6608 address = Rn;
6610 // data = MemU[address,2];
6616 context.SetRegisterPlusOffset (base_reg, address - Rn);
6618 uint64_t data = MemURead (context, address, 2, 0, &success);
6631 // if UnalignedSupport() || address<0> = '0' then
6632 if (UnalignedSupport () || BitIsClear (address, 0))
6636 context.SetRegisterPlusOffset (base_reg, address - Rn);
6649 // LDRH (literal) caculates an address from the PC value and an immediate offset, loads a halfword from memory,
6658 address = if add then (base + imm32) else (base - imm32);
6659 data = MemU[address,2];
6660 if UnalignedSupport() || address<0> = '0' then
6716 addr_t address;
6718 // address = if add then (base + imm32) else (base - imm32);
6720 address = base + imm32;
6722 address = base - imm32;
6724 // data = MemU[address,2];
6730 context.SetRegisterPlusOffset (base_reg, address - base);
6732 uint64_t data = MemURead (context, address, 2, 0, &success);
6737 // if UnalignedSupport() || address<0> = '0' then
6738 if (UnalignedSupport () || BitIsClear (address, 0))
6742 context.SetRegisterPlusOffset (base_reg, address - base);
6756 // LDRH (literal) calculates an address from a base register value and an offset register value, loads a halfword
6767 address = if index then offset_addr else R[n];
6768 data = MemU[address,2];
6770 if UnalignedSupport() || address<0> = '0' then
6873 addr_t address;
6885 // address = if index then offset_addr else R[n];
6887 address = offset_addr;
6889 address = Rn;
6891 // data = MemU[address,2];
6900 uint64_t data = MemURead (context, address, 2, 0, &success);
6913 // if UnalignedSupport() || address<0> = '0' then
6914 if (UnalignedSupport() || BitIsClear (address, 0))
6931 // LDRSB (immediate) calculates an address from a base register value and an immediate offset, loads a byte from
6941 address = if index then offset_addr else R[n];
6942 R[t] = SignExtend(MemU[address,1], 32);
7038 addr_t address;
7046 // address = if index then offset_addr else R[n];
7048 address = offset_addr;
7050 address = Rn;
7052 // R[t] = SignExtend(MemU[address,1], 32);
7058 context.SetRegisterPlusOffset (base_reg, address - Rn);
7060 uint64_t unsigned_data = MemURead (context, address, 1, 0, &success);
7081 // LDRSB (literal) calculates an address from the PC value and an immediate offset, loads a byte from memory,
7090 address = if add then (base + imm32) else (base - imm32);
7091 R[t] = SignExtend(MemU[address,1], 32);
7144 // address = if add then (base + imm32) else (base - imm32);
7145 addr_t address;
7147 address = base + imm32;
7149 address = base - imm32;
7151 // R[t] = SignExtend(MemU[address,1], 32);
7157 context.SetRegisterPlusOffset (base_reg, address - base);
7159 uint64_t unsigned_data = MemURead (context, address, 1, 0, &success);
7170 // LDRSB (register) calculates an address from a base register value and an offset register value, loadsa byte from
7181 address = if index then offset_addr else R[n];
7182 R[t] = SignExtend(MemU[address,1], 32);
7280 addr_t address;
7292 // address = if index then offset_addr else R[n];
7294 address = offset_addr;
7296 address = Rn;
7298 // R[t] = SignExtend(MemU[address,1], 32);
7308 uint64_t unsigned_data = MemURead (context, address, 1, 0, &success);
7328 // LDRSH (immediate) calculates an address from a base register value and an immediate offset, loads a halfword from
7338 address = if index then offset_addr else R[n];
7339 data = MemU[address,2];
7341 if UnalignedSupport() || address<0> = '0' then
7442 // address = if index then offset_addr else R[n];
7443 addr_t address;
7445 address = offset_addr;
7447 address = Rn;
7449 // data = MemU[address,2];
7455 context.SetRegisterPlusOffset (base_reg, address - Rn);
7457 uint64_t data = MemURead (context, address, 2, 0, &success);
7470 // if UnalignedSupport() || address<0> = '0' then
7471 if (UnalignedSupport() || BitIsClear (address, 0))
7476 context.SetRegisterPlusOffset (base_reg, address - Rn);
7489 // LDRSH (literal) calculates an address from the PC value and an immediate offset, loads a halfword from memory,
7498 address = if add then (base + imm32) else (base - imm32);
7499 data = MemU[address,2];
7500 if UnalignedSupport() || address<0> = '0' then
7556 addr_t address;
7557 // address = if add then (base + imm32) else (base - imm32);
7559 address = base + imm32;
7561 address = base - imm32;
7563 // data = MemU[address,2];
7571 uint64_t data = MemURead (context, address, 2, 0, &success);
7575 // if UnalignedSupport() || address<0> = '0' then
7576 if (UnalignedSupport() || BitIsClear (address, 0))
7592 // LDRSH (register) calculates an address from a base register value and an offset register value, loads a halfword
7603 address = if index then offset_addr else R[n];
7604 data = MemU[address,2];
7606 if UnalignedSupport() || address<0> = '0' then
7713 addr_t address;
7721 // address = if index then offset_addr else R[n];
7723 address = offset_addr;
7725 address = Rn;
7727 // data = MemU[address,2];
7738 uint64_t data = MemURead (context, address, 2, 0, &success);
7751 // if UnalignedSupport() || address<0> = '0' then
7752 if (UnalignedSupport() || BitIsClear (address, 0))
8102 // RFE (Return From Exception) loads the PC and the CPSR from the word at the specified address and the following
8113 address = if increment then R[n] else R[n]-8;
8114 if wordhigher then address = address+4;
8115 CPSRWriteByInstr(MemA[address+4,4], '1111', TRUE);
8116 BranchWritePC(MemA[address,4]);
8195 addr_t address;
8196 // address = if increment then R[n] else R[n]-8;
8198 address = Rn;
8200 address = Rn - 8;
8202 // if wordhigher then address = address+4;
8204 address = address + 4;
8206 // CPSRWriteByInstr(MemA[address+4,4], '1111', TRUE);
8212 context.SetRegisterPlusOffset (base_reg, address - Rn);
8214 uint64_t data = MemARead (context, address + 4, 4, 0, &success);
8220 // BranchWritePC(MemA[address,4]);
8221 uint64_t data2 = MemARead (context, address, 4, 0, &success);
9749 // Store Register Exclusive calculates an address from a base register value and an immediate offset, and stores a
9757 address = R[n] + imm32;
9758 if ExclusiveMonitorsPass(address,4) then
9759 MemA[address,4] = R[t];
9815 // address = R[n] + imm32;
9820 addr_t address = Rn + imm32;
9830 // if ExclusiveMonitorsPass(address,4) then
9831 // if (ExclusiveMonitorsPass (address, addr_byte_size)) -- For now, for the sake of emulation, we will say this
9835 // MemA[address,4] = R[t];
9840 if (!MemAWrite (context, address, Rt, addr_byte_size))
9865 address = if index then offset_addr else R[n];
9866 MemU[address,1] = R[t]<7:0>;
9920 // address = if index then offset_addr else R[n];
9921 addr_t address;
9923 address = offset_addr;
9925 address = Rn;
9927 // MemU[address,1] = R[t]<7:0>;
9938 context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, address - Rn);
9940 if (!MemUWrite (context, address, Bits32 (Rt, 7, 0), 1))
9961 address = if index then offset_addr else R[n];
9962 MemU[address,4] = if t == 15 then PCStoreValue() else R[t];
10015 // address = if index then offset_addr else R[n];
10016 addr_t address;
10018 address = offset_addr;
10020 address = Rn;
10028 context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, address - Rn);
10030 // MemU[address,4] = if t == 15 then PCStoreValue() else R[t];
10041 if (!MemUWrite (context, address, pc_value, addr_byte_size))
10046 if (!MemUWrite (context, address, Rt, addr_byte_size))
10064 // Load Register Dual (immediate) calculates an address from a base register value and an immediate offset, loads two
10073 address = if index then offset_addr else R[n];
10074 R[t] = MemA[address,4];
10075 R[t2] = MemA[address+4,4];
10162 //address = if index then offset_addr else R[n];
10163 addr_t address;
10165 address = offset_addr;
10167 address = Rn;
10169 //R[t] = MemA[address,4];
10175 context.SetRegisterPlusOffset (base_reg, address - Rn);
10178 uint32_t data = MemARead (context, address, addr_byte_size, 0, &success);
10185 //R[t2] = MemA[address+4,4];
10187 context.SetRegisterPlusOffset (base_reg, (address + 4) - Rn);
10188 data = MemARead (context, address + 4, addr_byte_size, 0, &success);
10209 // Load Register Dual (register) calculates an address from a base register value and a register offset, loads two
10218 address = if index then offset_addr else R[n];
10219 R[t] = MemA[address,4];
10220 R[t2] = MemA[address+4,4];
10293 // address = if index then offset_addr else R[n];
10294 addr_t address;
10296 address = offset_addr;
10298 address = Rn;
10304 // R[t] = MemA[address,4];
10306 uint32_t data = MemARead (context, address, addr_byte_size, 0, &success);
10313 // R[t2] = MemA[address+4,4];
10315 data = MemARead (context, address + 4, addr_byte_size, 0, &success);
10336 // Store Register Dual (immediate) calculates an address from a base register value and an immediate offset, and
10345 address = if index then offset_addr else R[n];
10346 MemA[address,4] = R[t];
10347 MemA[address+4,4] = R[t2];
10436 //address = if index then offset_addr else R[n];
10437 addr_t address;
10439 address = offset_addr;
10441 address = Rn;
10443 //MemA[address,4] = R[t];
10453 context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, address - Rn);
10457 if (!MemAWrite (context, address, data, addr_byte_size))
10460 //MemA[address+4,4] = R[t2];
10462 context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, (address + 4) - Rn);
10468 if (!MemAWrite (context, address + 4, data, addr_byte_size))
10493 address = if index then offset_addr else R[n];
10494 MemA[address,4] = R[t];
10495 MemA[address+4,4] = R[t2];
10572 // address = if index then offset_addr else R[n];
10573 addr_t address;
10575 address = offset_addr;
10577 address = Rn;
10578 // MemA[address,4] = R[t];
10590 if (!MemAWrite (context, address, Rt, addr_byte_size))
10593 // MemA[address+4,4] = R[t2];
10602 if (!MemAWrite (context, address + 4, Rt2, addr_byte_size))
10620 // Vector Load Multiple loads multiple extension registers from consecutive memory locations using an address from
10628 address = if add then R[n] else R[n]-imm32;
10632 S[d+r] = MemA[address,4]; address = address+4;
10634 word1 = MemA[address,4]; word2 = MemA[address+4,4]; address = address+8;
10727 // address = if add then R[n] else R[n]-imm32;
10728 addr_t address;
10730 address = Rn;
10732 address = Rn - imm32;
10762 // S[d+r] = MemA[address,4]; address = address+4;
10763 context.SetRegisterPlusOffset (base_reg, address - Rn);
10765 uint32_t data = MemARead (context, address, addr_byte_size, 0, &success);
10772 address = address + 4;
10776 // word1 = MemA[address,4]; word2 = MemA[address+4,4]; address = address+8;
10777 context.SetRegisterPlusOffset (base_reg, address - Rn);
10778 uint32_t word1 = MemARead (context, address, addr_byte_size, 0, &success);
10782 context.SetRegisterPlusOffset (base_reg, (address + 4) - Rn);
10783 uint32_t word2 = MemARead (context, address + 4, addr_byte_size, 0, &success);
10787 address = address + 8;
10811 // Vector Store Multiple stores multiple extension registers to consecutive memory locations using an address from an
10819 address = if add then R[n] else R[n]-imm32;
10823 MemA[address,4] = S[d+r]; address = address+4;
10826 MemA[address,4] = if BigEndian() then D[d+r]<63:32> else D[d+r]<31:0>;
10827 MemA[address+4,4] = if BigEndian() then D[d+r]<31:0> else D[d+r]<63:32>;
10828 address = address+8;
10920 // address = if add then R[n] else R[n]-imm32;
10921 addr_t address;
10923 address = Rn;
10925 address = Rn - imm32;
10954 // MemA[address,4] = S[d+r]; address = address+4;
10961 context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, address - Rn);
10962 if (!MemAWrite (context, address, data, addr_byte_size))
10965 address = address + 4;
10970 // MemA[address,4] = if BigEndian() then D[d+r]<63:32> else D[d+r]<31:0>;
10971 // MemA[address+4,4] = if BigEndian() then D[d+r]<31:0> else D[d+r]<63:32>;
10981 context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, address - Rn);
10982 if (!MemAWrite (context, address, Bits64 (data, 63, 32), addr_byte_size))
10985 address + 4) - Rn);
10986 if (!MemAWrite (context, address+ 4, Bits64 (data, 31, 0), addr_byte_size))
10991 context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, address - Rn);
10992 if (!MemAWrite (context, address, Bits64 (data, 31, 0), addr_byte_size))
10995 context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, (address + 4) - Rn);
10996 if (!MemAWrite (context, address + 4, Bits64 (data, 63, 32), addr_byte_size))
10999 // address = address+8;
11000 address = address + 8;
11008 // This instruciton loads a single extension register fronm memory, using an address from an ARM core register, with
11017 address = if add then (base + imm32) else (base - imm32);
11019 S[d] = MemA[address,4];
11021 word1 = MemA[address,4]; word2 = MemA[address+4,4];
11081 // address = if add then (base + imm32) else (base - imm32);
11082 addr_t address;
11084 address = base + imm32;
11086 address = base - imm32;
11093 context.SetRegisterPlusOffset (base_reg, address - base);
11097 // S[d] = MemA[address,4];
11098 uint32_t data = MemARead (context, address, addr_byte_size, 0, &success);
11107 // word1 = MemA[address,4]; word2 = MemA[address+4,4];
11108 uint32_t word1 = MemARead (context, address, addr_byte_size, 0, &success);
11112 context.SetRegisterPlusOffset (base_reg, (address + 4) - base);
11113 uint32_t word2 = MemARead (context, address + 4, addr_byte_size, 0, &success);
11138 // This instruction stores a signle extension register to memory, using an address from an ARM core register, with an
11146 address = if add then (R[n] + imm32) else (R[n] - imm32);
11148 MemA[address,4] = S[d];
11151 MemA[address,4] = if BigEndian() then D[d]<63:32> else D[d]<31:0>;
11152 MemA[address+4,4] = if BigEndian() then D[d]<31:0> else D[d]<63:32>;
11212 // address = if add then (R[n] + imm32) else (R[n] - imm32);
11213 addr_t address;
11215 address = Rn + imm32;
11217 address = Rn - imm32;
11226 context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, address - Rn);
11230 // MemA[address,4] = S[d];
11235 if (!MemAWrite (context, address, data, addr_byte_size))
11241 // MemA[address,4] = if BigEndian() then D[d]<63:32> else D[d]<31:0>;
11242 // MemA[address+4,4] = if BigEndian() then D[d]<31:0> else D[d]<63:32>;
11249 if (!MemAWrite (context, address, Bits64 (data, 63, 32), addr_byte_size))
11252 context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, (address + 4) - Rn);
11253 if (!MemAWrite (context, address + 4, Bits64 (data, 31, 0), addr_byte_size))
11258 if (!MemAWrite (context, address, Bits64 (data, 31, 0), addr_byte_size))
11261 context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, (address + 4) - Rn);
11262 if (!MemAWrite (context, address + 4, Bits64 (data, 63, 32), addr_byte_size))
11279 address = R[n]; if (address MOD alignment) != 0 then GenerateAlignmentException();
11283 Elem[D[d+r],e,esize] = MemU[address,ebytes];
11284 address = address + ebytes;
11383 // address = R[n]; if (address MOD alignment) != 0 then GenerateAlignmentException();
11384 addr_t address = Rn;
11385 if ((address % alignment) != 0)
11418 // Elem[D[d+r],e,esize] = MemU[address,ebytes];
11420 context.SetRegisterPlusOffset (base_reg, address - Rn);
11421 uint64_t data = MemURead (context, address, ebytes, 0, &success);
11427 // address = address + ebytes;
11428 address = address + ebytes;
11445 address = R[n]; if (address MOD alignment) != 0 then GenerateAlignmentException();
11447 Elem[D[d],index,esize] = MemU[address,ebytes];
11555 // address = R[n]; if (address MOD alignment) != 0 then GenerateAlignmentException();
11556 addr_t address = Rn;
11557 if ((address % alignment) != 0)
11583 // Elem[D[d],index,esize] = MemU[address,ebytes];
11584 uint32_t element = MemURead (context, address, esize, 0, &success);
11621 address = R[n]; if (address MOD alignment) != 0 then GenerateAlignmentException();
11625 MemU[address,ebytes] = Elem[D[d+r],e,esize];
11626 address = address + ebytes;
11722 // address = R[n]; if (address MOD alignment) != 0 then GenerateAlignmentException();
11723 addr_t address = Rn;
11724 if ((address % alignment) != 0)
11761 // MemU[address,ebytes] = Elem[D[d+r],e,esize];
11764 context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, address - Rn);
11765 if (!MemUWrite (context, address, word, ebytes))
11768 // address = address + ebytes;
11769 address = address + ebytes;
11784 address = R[n]; if (address MOD alignment) != 0 then GenerateAlignmentException();
11786 MemU[address,ebytes] = Elem[D[d],index,esize];
11894 // address = R[n]; if (address MOD alignment) != 0 then GenerateAlignmentException();
11895 addr_t address = Rn;
11896 if ((address % alignment) != 0)
11920 // MemU[address,ebytes] = Elem[D[d],index,esize];
11930 context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, address - Rn);
11932 if (!MemUWrite (context, address, word, ebytes))
11946 address = R[n]; if (address MOD alignment) != 0 then GenerateAlignmentException();
11948 replicated_element = Replicate(MemU[address,ebytes], elements);
12020 // address = R[n]; if (address MOD alignment) != 0 then GenerateAlignmentException();
12021 addr_t address = Rn;
12022 if ((address % alignment) != 0)
12046 // replicated_element = Replicate(MemU[address,ebytes], elements);
12049 uint64_t word = MemURead (context, address, ebytes, 0, &success);
12071 // immediate constant from the LR, branches to the resulting address, and also copies the SPSR to the CPSR.
12843 EmulateInstructionARM::SetInstruction (const Opcode &insn_opcode, const Address &inst_addr, Target *target)
13182 return false; // address<1:0> == '10' => UNPREDICTABLE
13315 // When executing an ARM instruction , PC reads as the address of the current
13317 // When executing a Thumb instruction , PC reads as the address of the current
13612 // Our previous Call Frame Address is the stack pointer
