Lines Matching refs:m_state
282 return m_state.context.gpr.__eip;
293 m_state.context.gpr.__eip = value;
304 return m_state.context.gpr.__esp;
310 //#define SET_GPR(reg) m_state.context.gpr.__##reg = gpr_##reg
315 if (force || m_state.GetError(e_regSetGPR, Read))
334 m_state.SetError(e_regSetGPR, Read, 0);
337 m_state.SetError(e_regSetGPR, Read, ::thread_get_state(m_thread->MachPortNumber(), __i386_THREAD_STATE, (thread_state_t)&m_state.context.gpr, &count));
340 return m_state.GetError(e_regSetGPR, Read);
349 if (force || m_state.GetError(e_regSetFPU, Read))
355 m_state.context.fpu.avx.__fpu_reserved[0] = -1;
356 m_state.context.fpu.avx.__fpu_reserved[1] = -1;
357 *(uint16_t *)&(m_state.context.fpu.avx.__fpu_fcw) = 0x1234;
358 *(uint16_t *)&(m_state.context.fpu.avx.__fpu_fsw) = 0x5678;
359 m_state.context.fpu.avx.__fpu_ftw = 1;
360 m_state.context.fpu.avx.__fpu_rsrv1 = UINT8_MAX;
361 m_state.context.fpu.avx.__fpu_fop = 2;
362 m_state.context.fpu.avx.__fpu_ip = 3;
363 m_state.context.fpu.avx.__fpu_cs = 4;
364 m_state.context.fpu.avx.__fpu_rsrv2 = 5;
365 m_state.context.fpu.avx.__fpu_dp = 6;
366 m_state.context.fpu.avx.__fpu_ds = 7;
367 m_state.context.fpu.avx.__fpu_rsrv3 = UINT16_MAX;
368 m_state.context.fpu.avx.__fpu_mxcsr = 8;
369 m_state.context.fpu.avx.__fpu_mxcsrmask = 9;
375 m_state.context.fpu.avx.__fpu_stmm0.__mmst_reg[i] = 'a';
376 m_state.context.fpu.avx.__fpu_stmm1.__mmst_reg[i] = 'b';
377 m_state.context.fpu.avx.__fpu_stmm2.__mmst_reg[i] = 'c';
378 m_state.context.fpu.avx.__fpu_stmm3.__mmst_reg[i] = 'd';
379 m_state.context.fpu.avx.__fpu_stmm4.__mmst_reg[i] = 'e';
380 m_state.context.fpu.avx.__fpu_stmm5.__mmst_reg[i] = 'f';
381 m_state.context.fpu.avx.__fpu_stmm6.__mmst_reg[i] = 'g';
382 m_state.context.fpu.avx.__fpu_stmm7.__mmst_reg[i] = 'h';
386 m_state.context.fpu.avx.__fpu_stmm0.__mmst_reg[i] = INT8_MIN;
387 m_state.context.fpu.avx.__fpu_stmm1.__mmst_reg[i] = INT8_MIN;
388 m_state.context.fpu.avx.__fpu_stmm2.__mmst_reg[i] = INT8_MIN;
389 m_state.context.fpu.avx.__fpu_stmm3.__mmst_reg[i] = INT8_MIN;
390 m_state.context.fpu.avx.__fpu_stmm4.__mmst_reg[i] = INT8_MIN;
391 m_state.context.fpu.avx.__fpu_stmm5.__mmst_reg[i] = INT8_MIN;
392 m_state.context.fpu.avx.__fpu_stmm6.__mmst_reg[i] = INT8_MIN;
393 m_state.context.fpu.avx.__fpu_stmm7.__mmst_reg[i] = INT8_MIN;
396 m_state.context.fpu.avx.__fpu_xmm0.__xmm_reg[i] = '0';
397 m_state.context.fpu.avx.__fpu_xmm1.__xmm_reg[i] = '1';
398 m_state.context.fpu.avx.__fpu_xmm2.__xmm_reg[i] = '2';
399 m_state.context.fpu.avx.__fpu_xmm3.__xmm_reg[i] = '3';
400 m_state.context.fpu.avx.__fpu_xmm4.__xmm_reg[i] = '4';
401 m_state.context.fpu.avx.__fpu_xmm5.__xmm_reg[i] = '5';
402 m_state.context.fpu.avx.__fpu_xmm6.__xmm_reg[i] = '6';
403 m_state.context.fpu.avx.__fpu_xmm7.__xmm_reg[i] = '7';
405 for (i=0; i<sizeof(m_state.context.fpu.avx.__fpu_rsrv4); ++i)
406 m_state.context.fpu.avx.__fpu_rsrv4[i] = INT8_MIN;
407 m_state.context.fpu.avx.__fpu_reserved1 = -1;
408 for (i=0; i<sizeof(m_state.context.fpu.avx.__avx_reserved1); ++i)
409 m_state.context.fpu.avx.__avx_reserved1[i] = INT8_MIN;
413 m_state.context.fpu.avx.__fpu_ymmh0.__xmm_reg[i] = '0';
414 m_state.context.fpu.avx.__fpu_ymmh1.__xmm_reg[i] = '1';
415 m_state.context.fpu.avx.__fpu_ymmh2.__xmm_reg[i] = '2';
416 m_state.context.fpu.avx.__fpu_ymmh3.__xmm_reg[i] = '3';
417 m_state.context.fpu.avx.__fpu_ymmh4.__xmm_reg[i] = '4';
418 m_state.context.fpu.avx.__fpu_ymmh5.__xmm_reg[i] = '5';
419 m_state.context.fpu.avx.__fpu_ymmh6.__xmm_reg[i] = '6';
420 m_state.context.fpu.avx.__fpu_ymmh7.__xmm_reg[i] = '7';
425 m_state.context.fpu.no_avx.__fpu_reserved[0] = -1;
426 m_state.context.fpu.no_avx.__fpu_reserved[1] = -1;
427 *(uint16_t *)&(m_state.context.fpu.no_avx.__fpu_fcw) = 0x1234;
428 *(uint16_t *)&(m_state.context.fpu.no_avx.__fpu_fsw) = 0x5678;
429 m_state.context.fpu.no_avx.__fpu_ftw = 1;
430 m_state.context.fpu.no_avx.__fpu_rsrv1 = UINT8_MAX;
431 m_state.context.fpu.no_avx.__fpu_fop = 2;
432 m_state.context.fpu.no_avx.__fpu_ip = 3;
433 m_state.context.fpu.no_avx.__fpu_cs = 4;
434 m_state.context.fpu.no_avx.__fpu_rsrv2 = 5;
435 m_state.context.fpu.no_avx.__fpu_dp = 6;
436 m_state.context.fpu.no_avx.__fpu_ds = 7;
437 m_state.context.fpu.no_avx.__fpu_rsrv3 = UINT16_MAX;
438 m_state.context.fpu.no_avx.__fpu_mxcsr = 8;
439 m_state.context.fpu.no_avx.__fpu_mxcsrmask = 9;
445 m_state.context.fpu.no_avx.__fpu_stmm0.__mmst_reg[i] = 'a';
446 m_state.context.fpu.no_avx.__fpu_stmm1.__mmst_reg[i] = 'b';
447 m_state.context.fpu.no_avx.__fpu_stmm2.__mmst_reg[i] = 'c';
448 m_state.context.fpu.no_avx.__fpu_stmm3.__mmst_reg[i] = 'd';
449 m_state.context.fpu.no_avx.__fpu_stmm4.__mmst_reg[i] = 'e';
450 m_state.context.fpu.no_avx.__fpu_stmm5.__mmst_reg[i] = 'f';
451 m_state.context.fpu.no_avx.__fpu_stmm6.__mmst_reg[i] = 'g';
452 m_state.context.fpu.no_avx.__fpu_stmm7.__mmst_reg[i] = 'h';
456 m_state.context.fpu.no_avx.__fpu_stmm0.__mmst_reg[i] = INT8_MIN;
457 m_state.context.fpu.no_avx.__fpu_stmm1.__mmst_reg[i] = INT8_MIN;
458 m_state.context.fpu.no_avx.__fpu_stmm2.__mmst_reg[i] = INT8_MIN;
459 m_state.context.fpu.no_avx.__fpu_stmm3.__mmst_reg[i] = INT8_MIN;
460 m_state.context.fpu.no_avx.__fpu_stmm4.__mmst_reg[i] = INT8_MIN;
461 m_state.context.fpu.no_avx.__fpu_stmm5.__mmst_reg[i] = INT8_MIN;
462 m_state.context.fpu.no_avx.__fpu_stmm6.__mmst_reg[i] = INT8_MIN;
463 m_state.context.fpu.no_avx.__fpu_stmm7.__mmst_reg[i] = INT8_MIN;
466 m_state.context.fpu.no_avx.__fpu_xmm0.__xmm_reg[i] = '0';
467 m_state.context.fpu.no_avx.__fpu_xmm1.__xmm_reg[i] = '1';
468 m_state.context.fpu.no_avx.__fpu_xmm2.__xmm_reg[i] = '2';
469 m_state.context.fpu.no_avx.__fpu_xmm3.__xmm_reg[i] = '3';
470 m_state.context.fpu.no_avx.__fpu_xmm4.__xmm_reg[i] = '4';
471 m_state.context.fpu.no_avx.__fpu_xmm5.__xmm_reg[i] = '5';
472 m_state.context.fpu.no_avx.__fpu_xmm6.__xmm_reg[i] = '6';
473 m_state.context.fpu.no_avx.__fpu_xmm7.__xmm_reg[i] = '7';
475 for (i=0; i<sizeof(m_state.context.fpu.avx.__fpu_rsrv4); ++i)
476 m_state.context.fpu.no_avx.__fpu_rsrv4[i] = INT8_MIN;
477 m_state.context.fpu.no_avx.__fpu_reserved1 = -1;
479 m_state.SetError(e_regSetFPU, Read, 0);
486 m_state.SetError (e_regSetFPU, Read, ::thread_get_state(m_thread->MachPortNumber(), __i386_AVX_STATE, (thread_state_t)&m_state.context.fpu.avx, &count));
489 m_state.GetError(e_regSetFPU, Read));
494 m_state.SetError(e_regSetFPU, Read, ::thread_get_state(m_thread->MachPortNumber(), __i386_FLOAT_STATE, (thread_state_t)&m_state.context.fpu.no_avx, &count));
497 m_state.GetError(e_regSetFPU, Read));
501 return m_state.GetError(e_regSetFPU, Read);
507 if (force || m_state.GetError(e_regSetEXC, Read))
510 m_state.SetError(e_regSetEXC, Read, ::thread_get_state(m_thread->MachPortNumber(), __i386_EXCEPTION_STATE, (thread_state_t)&m_state.context.exc, &count));
512 return m_state.GetError(e_regSetEXC, Read);
518 m_state.SetError(e_regSetGPR, Write, ::thread_set_state(m_thread->MachPortNumber(), __i386_THREAD_STATE, (thread_state_t)&m_state.context.gpr, e_regSetWordSizeGPR));
519 return m_state.GetError(e_regSetGPR, Write);
527 m_state.SetError(e_regSetFPU, Write, 0);
528 return m_state.GetError(e_regSetFPU, Write);
533 m_state.SetError(e_regSetFPU, Write, ::thread_set_state(m_thread->MachPortNumber(), __i386_AVX_STATE, (thread_state_t)&m_state.context.fpu.avx, e_regSetWordSizeAVX));
535 m_state.SetError(e_regSetFPU, Write, ::thread_set_state(m_thread->MachPortNumber(), __i386_FLOAT_STATE, (thread_state_t)&m_state.context.fpu.no_avx, e_regSetWordSizeFPU));
536 return m_state.GetError(e_regSetFPU, Write);
543 m_state.SetError(e_regSetEXC, Write, ::thread_set_state(m_thread->MachPortNumber(), __i386_EXCEPTION_STATE, (thread_state_t)&m_state.context.exc, e_regSetWordSizeEXC));
544 return m_state.GetError(e_regSetEXC, Write);
550 if (force || m_state.GetError(e_regSetDBG, Read))
553 m_state.SetError(e_regSetDBG, Read, ::thread_get_state(m_thread->MachPortNumber(), __i386_DEBUG_STATE, (thread_state_t)&m_state.context.dbg, &count));
555 return m_state.GetError(e_regSetDBG, Read);
561 m_state.SetError(e_regSetDBG, Write, ::thread_set_state(m_thread->MachPortNumber(), __i386_DEBUG_STATE, (thread_state_t)&m_state.context.dbg, e_regSetWordSizeDBG));
564 kern_return_t kret = ::task_set_state(m_thread->Process()->Task().TaskPort(), __i386_DEBUG_STATE, (thread_state_t)&m_state.context.dbg, e_regSetWordSizeDBG);
569 return m_state.GetError(e_regSetDBG, Write);
588 DBG &debug_state = m_state.context.dbg;
608 m_state.InvalidateAllRegisterStates();
662 if (m_state.context.gpr.__eip > 0)
664 m_state.context.gpr.__eip = pc;
853 m_2pc_dbg_checkpoint = m_state.context.dbg;
860 m_state.context.dbg = m_2pc_dbg_checkpoint;
907 DBG &debug_state = m_state.context.dbg;
928 m_state.context.dbg = GetDBGCheckpoint();
946 DBG &debug_state = m_state.context.dbg;
961 m_state.context.dbg = GetDBGCheckpoint();
976 DBG &debug_state = m_state.context.dbg;
1001 m_state.context.gpr.__eflags |= trace_bit;
1003 m_state.context.gpr.__eflags &= ~trace_bit;
1006 return m_state.GetError(e_regSetGPR, Read);
1308 value->value.uint32 = ((uint32_t*)(&m_state.context.gpr))[reg];
1318 case fpu_fcw: value->value.uint16 = *((uint16_t *)(&m_state.context.fpu.avx.__fpu_fcw)); return true;
1319 case fpu_fsw: value->value.uint16 = *((uint16_t *)(&m_state.context.fpu.avx.__fpu_fsw)); return true;
1320 case fpu_ftw: value->value.uint8 = m_state.context.fpu.avx.__fpu_ftw; return true;
1321 case fpu_fop: value->value.uint16 = m_state.context.fpu.avx.__fpu_fop; return true;
1322 case fpu_ip: value->value.uint32 = m_state.context.fpu.avx.__fpu_ip; return true;
1323 case fpu_cs: value->value.uint16 = m_state.context.fpu.avx.__fpu_cs; return true;
1324 case fpu_dp: value->value.uint32 = m_state.context.fpu.avx.__fpu_dp; return true;
1325 case fpu_ds: value->value.uint16 = m_state.context.fpu.avx.__fpu_ds; return true;
1326 case fpu_mxcsr: value->value.uint32 = m_state.context.fpu.avx.__fpu_mxcsr; return true;
1327 case fpu_mxcsrmask: value->value.uint32 = m_state.context.fpu.avx.__fpu_mxcsrmask; return true;
1329 case fpu_stmm0: memcpy(&value->value.uint8, m_state.context.fpu.avx.__fpu_stmm0.__mmst_reg, 10); return true;
1330 case fpu_stmm1: memcpy(&value->value.uint8, m_state.context.fpu.avx.__fpu_stmm1.__mmst_reg, 10); return true;
1331 case fpu_stmm2: memcpy(&value->value.uint8, m_state.context.fpu.avx.__fpu_stmm2.__mmst_reg, 10); return true;
1332 case fpu_stmm3: memcpy(&value->value.uint8, m_state.context.fpu.avx.__fpu_stmm3.__mmst_reg, 10); return true;
1333 case fpu_stmm4: memcpy(&value->value.uint8, m_state.context.fpu.avx.__fpu_stmm4.__mmst_reg, 10); return true;
1334 case fpu_stmm5: memcpy(&value->value.uint8, m_state.context.fpu.avx.__fpu_stmm5.__mmst_reg, 10); return true;
1335 case fpu_stmm6: memcpy(&value->value.uint8, m_state.context.fpu.avx.__fpu_stmm6.__mmst_reg, 10); return true;
1336 case fpu_stmm7: memcpy(&value->value.uint8, m_state.context.fpu.avx.__fpu_stmm7.__mmst_reg, 10); return true;
1338 case fpu_xmm0: memcpy(&value->value.uint8, m_state.context.fpu.avx.__fpu_xmm0.__xmm_reg, 16); return true;
1339 case fpu_xmm1: memcpy(&value->value.uint8, m_state.context.fpu.avx.__fpu_xmm1.__xmm_reg, 16); return true;
1340 case fpu_xmm2: memcpy(&value->value.uint8, m_state.context.fpu.avx.__fpu_xmm2.__xmm_reg, 16); return true;
1341 case fpu_xmm3: memcpy(&value->value.uint8, m_state.context.fpu.avx.__fpu_xmm3.__xmm_reg, 16); return true;
1342 case fpu_xmm4: memcpy(&value->value.uint8, m_state.context.fpu.avx.__fpu_xmm4.__xmm_reg, 16); return true;
1343 case fpu_xmm5: memcpy(&value->value.uint8, m_state.context.fpu.avx.__fpu_xmm5.__xmm_reg, 16); return true;
1344 case fpu_xmm6: memcpy(&value->value.uint8, m_state.context.fpu.avx.__fpu_xmm6.__xmm_reg, 16); return true;
1345 case fpu_xmm7: memcpy(&value->value.uint8, m_state.context.fpu.avx.__fpu_xmm7.__xmm_reg, 16); return true;
1348 memcpy(&value->value.uint8, m_state.context.fpu.avx.__fpu_xmm##n.__xmm_reg, 16); \
1349 memcpy((&value->value.uint8) + 16, m_state.context.fpu.avx.__fpu_ymmh##n.__xmm_reg, 16);
1365 case fpu_fcw: value->value.uint16 = *((uint16_t *)(&m_state.context.fpu.no_avx.__fpu_fcw)); return true;
1366 case fpu_fsw: value->value.uint16 = *((uint16_t *)(&m_state.context.fpu.no_avx.__fpu_fsw)); return true;
1367 case fpu_ftw: value->value.uint8 = m_state.context.fpu.no_avx.__fpu_ftw; return true;
1368 case fpu_fop: value->value.uint16 = m_state.context.fpu.no_avx.__fpu_fop; return true;
1369 case fpu_ip: value->value.uint32 = m_state.context.fpu.no_avx.__fpu_ip; return true;
1370 case fpu_cs: value->value.uint16 = m_state.context.fpu.no_avx.__fpu_cs; return true;
1371 case fpu_dp: value->value.uint32 = m_state.context.fpu.no_avx.__fpu_dp; return true;
1372 case fpu_ds: value->value.uint16 = m_state.context.fpu.no_avx.__fpu_ds; return true;
1373 case fpu_mxcsr: value->value.uint32 = m_state.context.fpu.no_avx.__fpu_mxcsr; return true;
1374 case fpu_mxcsrmask: value->value.uint32 = m_state.context.fpu.no_avx.__fpu_mxcsrmask; return true;
1376 case fpu_stmm0: memcpy(&value->value.uint8, m_state.context.fpu.no_avx.__fpu_stmm0.__mmst_reg, 10); return true;
1377 case fpu_stmm1: memcpy(&value->value.uint8, m_state.context.fpu.no_avx.__fpu_stmm1.__mmst_reg, 10); return true;
1378 case fpu_stmm2: memcpy(&value->value.uint8, m_state.context.fpu.no_avx.__fpu_stmm2.__mmst_reg, 10); return true;
1379 case fpu_stmm3: memcpy(&value->value.uint8, m_state.context.fpu.no_avx.__fpu_stmm3.__mmst_reg, 10); return true;
1380 case fpu_stmm4: memcpy(&value->value.uint8, m_state.context.fpu.no_avx.__fpu_stmm4.__mmst_reg, 10); return true;
1381 case fpu_stmm5: memcpy(&value->value.uint8, m_state.context.fpu.no_avx.__fpu_stmm5.__mmst_reg, 10); return true;
1382 case fpu_stmm6: memcpy(&value->value.uint8, m_state.context.fpu.no_avx.__fpu_stmm6.__mmst_reg, 10); return true;
1383 case fpu_stmm7: memcpy(&value->value.uint8, m_state.context.fpu.no_avx.__fpu_stmm7.__mmst_reg, 10); return true;
1385 case fpu_xmm0: memcpy(&value->value.uint8, m_state.context.fpu.no_avx.__fpu_xmm0.__xmm_reg, 16); return true;
1386 case fpu_xmm1: memcpy(&value->value.uint8, m_state.context.fpu.no_avx.__fpu_xmm1.__xmm_reg, 16); return true;
1387 case fpu_xmm2: memcpy(&value->value.uint8, m_state.context.fpu.no_avx.__fpu_xmm2.__xmm_reg, 16); return true;
1388 case fpu_xmm3: memcpy(&value->value.uint8, m_state.context.fpu.no_avx.__fpu_xmm3.__xmm_reg, 16); return true;
1389 case fpu_xmm4: memcpy(&value->value.uint8, m_state.context.fpu.no_avx.__fpu_xmm4.__xmm_reg, 16); return true;
1390 case fpu_xmm5: memcpy(&value->value.uint8, m_state.context.fpu.no_avx.__fpu_xmm5.__xmm_reg, 16); return true;
1391 case fpu_xmm6: memcpy(&value->value.uint8, m_state.context.fpu.no_avx.__fpu_xmm6.__xmm_reg, 16); return true;
1392 case fpu_xmm7: memcpy(&value->value.uint8, m_state.context.fpu.no_avx.__fpu_xmm7.__xmm_reg, 16); return true;
1400 value->value.uint32 = (&m_state.context.exc.__trapno)[reg];
1455 ((uint32_t*)(&m_state.context.gpr))[reg] = value->value.uint32;
1465 case fpu_fcw: *((uint16_t *)(&m_state.context.fpu.avx.__fpu_fcw)) = value->value.uint16; success = true; break;
1466 case fpu_fsw: *((uint16_t *)(&m_state.context.fpu.avx.__fpu_fsw)) = value->value.uint16; success = true; break;
1467 case fpu_ftw: m_state.context.fpu.avx.__fpu_ftw = value->value.uint8; success = true; break;
1468 case fpu_fop: m_state.context.fpu.avx.__fpu_fop = value->value.uint16; success = true; break;
1469 case fpu_ip: m_state.context.fpu.avx.__fpu_ip = value->value.uint32; success = true; break;
1470 case fpu_cs: m_state.context.fpu.avx.__fpu_cs = value->value.uint16; success = true; break;
1471 case fpu_dp: m_state.context.fpu.avx.__fpu_dp = value->value.uint32; success = true; break;
1472 case fpu_ds: m_state.context.fpu.avx.__fpu_ds = value->value.uint16; success = true; break;
1473 case fpu_mxcsr: m_state.context.fpu.avx.__fpu_mxcsr = value->value.uint32; success = true; break;
1474 case fpu_mxcsrmask: m_state.context.fpu.avx.__fpu_mxcsrmask = value->value.uint32; success = true; break;
1476 case fpu_stmm0: memcpy (m_state.context.fpu.avx.__fpu_stmm0.__mmst_reg, &value->value.uint8, 10); success = true; break;
1477 case fpu_stmm1: memcpy (m_state.context.fpu.avx.__fpu_stmm1.__mmst_reg, &value->value.uint8, 10); success = true; break;
1478 case fpu_stmm2: memcpy (m_state.context.fpu.avx.__fpu_stmm2.__mmst_reg, &value->value.uint8, 10); success = true; break;
1479 case fpu_stmm3: memcpy (m_state.context.fpu.avx.__fpu_stmm3.__mmst_reg, &value->value.uint8, 10); success = true; break;
1480 case fpu_stmm4: memcpy (m_state.context.fpu.avx.__fpu_stmm4.__mmst_reg, &value->value.uint8, 10); success = true; break;
1481 case fpu_stmm5: memcpy (m_state.context.fpu.avx.__fpu_stmm5.__mmst_reg, &value->value.uint8, 10); success = true; break;
1482 case fpu_stmm6: memcpy (m_state.context.fpu.avx.__fpu_stmm6.__mmst_reg, &value->value.uint8, 10); success = true; break;
1483 case fpu_stmm7: memcpy (m_state.context.fpu.avx.__fpu_stmm7.__mmst_reg, &value->value.uint8, 10); success = true; break;
1485 case fpu_xmm0: memcpy(m_state.context.fpu.avx.__fpu_xmm0.__xmm_reg, &value->value.uint8, 16); success = true; break;
1486 case fpu_xmm1: memcpy(m_state.context.fpu.avx.__fpu_xmm1.__xmm_reg, &value->value.uint8, 16); success = true; break;
1487 case fpu_xmm2: memcpy(m_state.context.fpu.avx.__fpu_xmm2.__xmm_reg, &value->value.uint8, 16); success = true; break;
1488 case fpu_xmm3: memcpy(m_state.context.fpu.avx.__fpu_xmm3.__xmm_reg, &value->value.uint8, 16); success = true; break;
1489 case fpu_xmm4: memcpy(m_state.context.fpu.avx.__fpu_xmm4.__xmm_reg, &value->value.uint8, 16); success = true; break;
1490 case fpu_xmm5: memcpy(m_state.context.fpu.avx.__fpu_xmm5.__xmm_reg, &value->value.uint8, 16); success = true; break;
1491 case fpu_xmm6: memcpy(m_state.context.fpu.avx.__fpu_xmm6.__xmm_reg, &value->value.uint8, 16); success = true; break;
1492 case fpu_xmm7: memcpy(m_state.context.fpu.avx.__fpu_xmm7.__xmm_reg, &value->value.uint8, 16); success = true; break;
1495 memcpy(m_state.context.fpu.avx.__fpu_xmm##n.__xmm_reg, &value->value.uint8, 16); \
1496 memcpy(m_state.context.fpu.avx.__fpu_ymmh##n.__xmm_reg, (&value->value.uint8) + 16, 16);
1512 case fpu_fcw: *((uint16_t *)(&m_state.context.fpu.no_avx.__fpu_fcw)) = value->value.uint16; success = true; break;
1513 case fpu_fsw: *((uint16_t *)(&m_state.context.fpu.no_avx.__fpu_fsw)) = value->value.uint16; success = true; break;
1514 case fpu_ftw: m_state.context.fpu.no_avx.__fpu_ftw = value->value.uint8; success = true; break;
1515 case fpu_fop: m_state.context.fpu.no_avx.__fpu_fop = value->value.uint16; success = true; break;
1516 case fpu_ip: m_state.context.fpu.no_avx.__fpu_ip = value->value.uint32; success = true; break;
1517 case fpu_cs: m_state.context.fpu.no_avx.__fpu_cs = value->value.uint16; success = true; break;
1518 case fpu_dp: m_state.context.fpu.no_avx.__fpu_dp = value->value.uint32; success = true; break;
1519 case fpu_ds: m_state.context.fpu.no_avx.__fpu_ds = value->value.uint16; success = true; break;
1520 case fpu_mxcsr: m_state.context.fpu.no_avx.__fpu_mxcsr = value->value.uint32; success = true; break;
1521 case fpu_mxcsrmask: m_state.context.fpu.no_avx.__fpu_mxcsrmask = value->value.uint32; success = true; break;
1523 case fpu_stmm0: memcpy (m_state.context.fpu.no_avx.__fpu_stmm0.__mmst_reg, &value->value.uint8, 10); success = true; break;
1524 case fpu_stmm1: memcpy (m_state.context.fpu.no_avx.__fpu_stmm1.__mmst_reg, &value->value.uint8, 10); success = true; break;
1525 case fpu_stmm2: memcpy (m_state.context.fpu.no_avx.__fpu_stmm2.__mmst_reg, &value->value.uint8, 10); success = true; break;
1526 case fpu_stmm3: memcpy (m_state.context.fpu.no_avx.__fpu_stmm3.__mmst_reg, &value->value.uint8, 10); success = true; break;
1527 case fpu_stmm4: memcpy (m_state.context.fpu.no_avx.__fpu_stmm4.__mmst_reg, &value->value.uint8, 10); success = true; break;
1528 case fpu_stmm5: memcpy (m_state.context.fpu.no_avx.__fpu_stmm5.__mmst_reg, &value->value.uint8, 10); success = true; break;
1529 case fpu_stmm6: memcpy (m_state.context.fpu.no_avx.__fpu_stmm6.__mmst_reg, &value->value.uint8, 10); success = true; break;
1530 case fpu_stmm7: memcpy (m_state.context.fpu.no_avx.__fpu_stmm7.__mmst_reg, &value->value.uint8, 10); success = true; break;
1532 case fpu_xmm0: memcpy(m_state.context.fpu.no_avx.__fpu_xmm0.__xmm_reg, &value->value.uint8, 16); success = true; break;
1533 case fpu_xmm1: memcpy(m_state.context.fpu.no_avx.__fpu_xmm1.__xmm_reg, &value->value.uint8, 16); success = true; break;
1534 case fpu_xmm2: memcpy(m_state.context.fpu.no_avx.__fpu_xmm2.__xmm_reg, &value->value.uint8, 16); success = true; break;
1535 case fpu_xmm3: memcpy(m_state.context.fpu.no_avx.__fpu_xmm3.__xmm_reg, &value->value.uint8, 16); success = true; break;
1536 case fpu_xmm4: memcpy(m_state.context.fpu.no_avx.__fpu_xmm4.__xmm_reg, &value->value.uint8, 16); success = true; break;
1537 case fpu_xmm5: memcpy(m_state.context.fpu.no_avx.__fpu_xmm5.__xmm_reg, &value->value.uint8, 16); success = true; break;
1538 case fpu_xmm6: memcpy(m_state.context.fpu.no_avx.__fpu_xmm6.__xmm_reg, &value->value.uint8, 16); success = true; break;
1539 case fpu_xmm7: memcpy(m_state.context.fpu.no_avx.__fpu_xmm7.__xmm_reg, &value->value.uint8, 16); success = true; break;
1547 (&m_state.context.exc.__trapno)[reg] = value->value.uint32;
1563 nub_size_t size = sizeof (m_state.context);
1590 ::memcpy (buf, &m_state.context, size);
1601 nub_size_t size = sizeof (m_state.context);
1610 ::memcpy (&m_state.context, buf, size);
1660 return m_state.RegsAreValid(set);
