Lines Matching refs:tii
278 const TargetInstrInfo *TII,
308 const MCInstrDesc Desc = TII->get(Opcode);
309 const TargetRegisterClass *RC = TII->getRegClass(Desc, Idx, TRI, MF);
410 const TargetInstrInfo *TII) {
420 if (IsChainDependent(N->getOperand(i).getNode(), Inner, NestLevel, TII))
427 (unsigned)TII->getCallFrameDestroyOpcode()) {
430 (unsigned)TII->getCallFrameSetupOpcode()) {
460 const TargetInstrInfo *TII) {
472 MyNestLevel, MyMaxNest, TII))
485 (unsigned)TII->getCallFrameDestroyOpcode()) {
489 (unsigned)TII->getCallFrameSetupOpcode()) {
554 Node->getMachineOpcode() == (unsigned)TII->getCallFrameDestroyOpcode()) {
557 SDNode *N = FindCallSeqStart(Node, NestLevel, MaxNest, TII);
759 SUNode->getMachineOpcode() == (unsigned)TII->getCallFrameSetupOpcode()) {
830 SUNode->getMachineOpcode() == (unsigned)TII->getCallFrameSetupOpcode()) {
843 SUNode->getMachineOpcode() == (unsigned)TII->getCallFrameDestroyOpcode()) {
964 if (!TII->unfoldMemoryOperand(*DAG, N, NewNodes))
1004 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
1193 const TargetInstrInfo *TII) {
1194 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
1306 if (Node->getMachineOpcode() == (unsigned)TII->getCallFrameDestroyOpcode()) {
1313 if (!IsChainDependent(Gen, Node, 0, TII) && RegAdded.insert(CallResource))
1320 const MCInstrDesc &MCID = TII->get(Node->getMachineOpcode());
1442 EVT VT = getPhysicalRegisterVT(LRDef->getNode(), Reg, TII);
1625 const TargetInstrInfo *TII;
1646 const TargetInstrInfo *tii,
1651 MF(mf), TII(tii), TRI(tri), TLI(tli), scheduleDAG(nullptr) {
1766 const TargetInstrInfo *tii,
1770 tii, tri, tli),
1956 GetCostForDef(RegDefPos, TLI, TII, TRI, RCId, Cost, MF);
1971 unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs();
2018 unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs();
2070 GetCostForDef(RegDefPos, TLI, TII, TRI, RCId, Cost, MF);
2085 GetCostForDef(RegDefPos, TLI, TII, TRI, RCId, Cost, MF);
2148 unsigned NumDefs = TII->get(PN->getMachineOpcode()).getNumDefs();
2165 unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs();
2685 const MCInstrDesc &MCID = TII->get(Opc);
2705 const TargetInstrInfo *TII,
2708 = TII->get(SU->getNode()->getMachineOpcode()).getImplicitDefs();
2741 const TargetInstrInfo *TII,
2744 unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs();
2745 const uint16_t *ImpDefs = TII->get(N->getMachineOpcode()).getImplicitDefs();
2752 TII->get(SUNode->getMachineOpcode()).getImplicitDefs();
2864 if (canClobberPhysRegDefs(PredSuccSU, SU, TII, TRI))
2912 const MCInstrDesc &MCID = TII->get(Opc);
2949 if (canClobberPhysRegDefs(SuccSU, SU, TII, TRI))
2959 if (!canClobberReachingPhysRegUse(SuccSU, SU, scheduleDAG, TII, TRI) &&
2981 const TargetInstrInfo *TII = TM.getInstrInfo();
2985 new BURegReductionPriorityQueue(*IS->MF, false, false, TII, TRI, nullptr);
2995 const TargetInstrInfo *TII = TM.getInstrInfo();
2999 new SrcRegReductionPriorityQueue(*IS->MF, false, true, TII, TRI, nullptr);
3009 const TargetInstrInfo *TII = TM.getInstrInfo();
3014 new HybridBURRPriorityQueue(*IS->MF, true, false, TII, TRI, TLI);
3025 const TargetInstrInfo *TII = TM.getInstrInfo();
3030 new ILPBURRPriorityQueue(*IS->MF, true, false, TII, TRI, TLI);
