Lines Matching refs:MVT
421 if (OpVT == MVT::f32) {
422 if (RetVT == MVT::f64)
424 if (RetVT == MVT::f128)
426 } else if (OpVT == MVT::f64) {
427 if (RetVT == MVT::f128)
437 if (RetVT == MVT::f32) {
438 if (OpVT == MVT::f64)
440 if (OpVT == MVT::f80)
442 if (OpVT == MVT::f128)
444 if (OpVT == MVT::ppcf128)
446 } else if (RetVT == MVT::f64) {
447 if (OpVT == MVT::f80)
449 if (OpVT == MVT::f128)
451 if (OpVT == MVT::ppcf128)
461 if (OpVT == MVT::f32) {
462 if (RetVT == MVT::i8)
464 if (RetVT == MVT::i16)
466 if (RetVT == MVT::i32)
468 if (RetVT == MVT::i64)
470 if (RetVT == MVT::i128)
472 } else if (OpVT == MVT::f64) {
473 if (RetVT == MVT::i8)
475 if (RetVT == MVT::i16)
477 if (RetVT == MVT::i32)
479 if (RetVT == MVT::i64)
481 if (RetVT == MVT::i128)
483 } else if (OpVT == MVT::f80) {
484 if (RetVT == MVT::i32)
486 if (RetVT == MVT::i64)
488 if (RetVT == MVT::i128)
490 } else if (OpVT == MVT::f128) {
491 if (RetVT == MVT::i32)
493 if (RetVT == MVT::i64)
495 if (RetVT == MVT::i128)
497 } else if (OpVT == MVT::ppcf128) {
498 if (RetVT == MVT::i32)
500 if (RetVT == MVT::i64)
502 if (RetVT == MVT::i128)
511 if (OpVT == MVT::f32) {
512 if (RetVT == MVT::i8)
514 if (RetVT == MVT::i16)
516 if (RetVT == MVT::i32)
518 if (RetVT == MVT::i64)
520 if (RetVT == MVT::i128)
522 } else if (OpVT == MVT::f64) {
523 if (RetVT == MVT::i8)
525 if (RetVT == MVT::i16)
527 if (RetVT == MVT::i32)
529 if (RetVT == MVT::i64)
531 if (RetVT == MVT::i128)
533 } else if (OpVT == MVT::f80) {
534 if (RetVT == MVT::i32)
536 if (RetVT == MVT::i64)
538 if (RetVT == MVT::i128)
540 } else if (OpVT == MVT::f128) {
541 if (RetVT == MVT::i32)
543 if (RetVT == MVT::i64)
545 if (RetVT == MVT::i128)
547 } else if (OpVT == MVT::ppcf128) {
548 if (RetVT == MVT::i32)
550 if (RetVT == MVT::i64)
552 if (RetVT == MVT::i128)
561 if (OpVT == MVT::i32) {
562 if (RetVT == MVT::f32)
564 if (RetVT == MVT::f64)
566 if (RetVT == MVT::f80)
568 if (RetVT == MVT::f128)
570 if (RetVT == MVT::ppcf128)
572 } else if (OpVT == MVT::i64) {
573 if (RetVT == MVT::f32)
575 if (RetVT == MVT::f64)
577 if (RetVT == MVT::f80)
579 if (RetVT == MVT::f128)
581 if (RetVT == MVT::ppcf128)
583 } else if (OpVT == MVT::i128) {
584 if (RetVT == MVT::f32)
586 if (RetVT == MVT::f64)
588 if (RetVT == MVT::f80)
590 if (RetVT == MVT::f128)
592 if (RetVT == MVT::ppcf128)
601 if (OpVT == MVT::i32) {
602 if (RetVT == MVT::f32)
604 if (RetVT == MVT::f64)
606 if (RetVT == MVT::f80)
608 if (RetVT == MVT::f128)
610 if (RetVT == MVT::ppcf128)
612 } else if (OpVT == MVT::i64) {
613 if (RetVT == MVT::f32)
615 if (RetVT == MVT::f64)
617 if (RetVT == MVT::f80)
619 if (RetVT == MVT::f128)
621 if (RetVT == MVT::ppcf128)
623 } else if (OpVT == MVT::i128) {
624 if (RetVT == MVT::f32)
626 if (RetVT == MVT::f64)
628 if (RetVT == MVT::f80)
630 if (RetVT == MVT::f128)
632 if (RetVT == MVT::ppcf128)
722 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
726 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) {
730 setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand);
731 setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand);
736 (MVT::SimpleValueType)VT, Expand);
739 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand);
740 setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand);
743 setOperationAction(ISD::FROUND, (MVT::SimpleValueType)VT, Expand);
746 if (VT >= MVT::FIRST_VECTOR_VALUETYPE &&
747 VT <= MVT::LAST_VECTOR_VALUETYPE) {
748 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
750 (MVT::SimpleValueType)VT, Expand);
752 (MVT::SimpleValueType)VT, Expand);
754 (MVT::SimpleValueType)VT, Expand);
759 setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
764 setOperationAction(ISD::ConstantFP, MVT::f16, Expand);
765 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
766 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
767 setOperationAction(ISD::ConstantFP, MVT::f80, Expand);
768 setOperationAction(ISD::ConstantFP, MVT::f128, Expand);
771 setOperationAction(ISD::FLOG , MVT::f16, Expand);
772 setOperationAction(ISD::FLOG2, MVT::f16, Expand);
773 setOperationAction(ISD::FLOG10, MVT::f16, Expand);
774 setOperationAction(ISD::FEXP , MVT::f16, Expand);
775 setOperationAction(ISD::FEXP2, MVT::f16, Expand);
776 setOperationAction(ISD::FFLOOR, MVT::f16, Expand);
777 setOperationAction(ISD::FNEARBYINT, MVT::f16, Expand);
778 setOperationAction(ISD::FCEIL, MVT::f16, Expand);
779 setOperationAction(ISD::FRINT, MVT::f16, Expand);
780 setOperationAction(ISD::FTRUNC, MVT::f16, Expand);
781 setOperationAction(ISD::FROUND, MVT::f16, Expand);
782 setOperationAction(ISD::FLOG , MVT::f32, Expand);
783 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
784 setOperationAction(ISD::FLOG10, MVT::f32, Expand);
785 setOperationAction(ISD::FEXP , MVT::f32, Expand);
786 setOperationAction(ISD::FEXP2, MVT::f32, Expand);
787 setOperationAction(ISD::FFLOOR, MVT::f32, Expand);
788 setOperationAction(ISD::FNEARBYINT, MVT::f32, Expand);
789 setOperationAction(ISD::FCEIL, MVT::f32, Expand);
790 setOperationAction(ISD::FRINT, MVT::f32, Expand);
791 setOperationAction(ISD::FTRUNC, MVT::f32, Expand);
792 setOperationAction(ISD::FROUND, MVT::f32, Expand);
793 setOperationAction(ISD::FLOG , MVT::f64, Expand);
794 setOperationAction(ISD::FLOG2, MVT::f64, Expand);
795 setOperationAction(ISD::FLOG10, MVT::f64, Expand);
796 setOperationAction(ISD::FEXP , MVT::f64, Expand);
797 setOperationAction(ISD::FEXP2, MVT::f64, Expand);
798 setOperationAction(ISD::FFLOOR, MVT::f64, Expand);
799 setOperationAction(ISD::FNEARBYINT, MVT::f64, Expand);
800 setOperationAction(ISD::FCEIL, MVT::f64, Expand);
801 setOperationAction(ISD::FRINT, MVT::f64, Expand);
802 setOperationAction(ISD::FTRUNC, MVT::f64, Expand);
803 setOperationAction(ISD::FROUND, MVT::f64, Expand);
804 setOperationAction(ISD::FLOG , MVT::f128, Expand);
805 setOperationAction(ISD::FLOG2, MVT::f128, Expand);
806 setOperationAction(ISD::FLOG10, MVT::f128, Expand);
807 setOperationAction(ISD::FEXP , MVT::f128, Expand);
808 setOperationAction(ISD::FEXP2, MVT::f128, Expand);
809 setOperationAction(ISD::FFLOOR, MVT::f128, Expand);
810 setOperationAction(ISD::FNEARBYINT, MVT::f128, Expand);
811 setOperationAction(ISD::FCEIL, MVT::f128, Expand);
812 setOperationAction(ISD::FRINT, MVT::f128, Expand);
813 setOperationAction(ISD::FTRUNC, MVT::f128, Expand);
814 setOperationAction(ISD::FROUND, MVT::f128, Expand);
817 setOperationAction(ISD::TRAP, MVT::Other, Expand);
822 MVT::Other, Expand);
825 MVT TargetLoweringBase::getPointerTy(uint32_t AS) const {
826 return MVT::getIntegerVT(getPointerSizeInBits(AS));
838 MVT TargetLoweringBase::getScalarShiftAmountTy(EVT LHSTy) const {
839 return MVT::getIntegerVT(8*DL->getPointerSize(0));
867 static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
869 MVT &RegisterVT,
873 MVT EltTy = VT.getVectorElementType();
886 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) {
893 MVT NewVT = MVT::getVectorVT(EltTy, NumElts);
904 MVT DestVT = TLI->getRegisterType(NewVT);
980 TargetLoweringBase::findRepresentativeClass(MVT VT) const {
1008 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE &&
1012 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
1014 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
1017 NumRegistersForVT[MVT::isVoid] = 0;
1020 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
1022 assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
1027 ExpandedReg <= MVT::LAST_INTEGER_VALUETYPE; ++ExpandedReg) {
1029 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
1030 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
1031 ValueTypeActions.setTypeAction((MVT::SimpleValueType)ExpandedReg,
1039 IntReg >= (unsigned)MVT::i1; --IntReg) {
1040 MVT IVT = (MVT::SimpleValueType)IntReg;
1045 (const MVT::SimpleValueType)LegalIntReg;
1051 if (!isTypeLegal(MVT::ppcf128)) {
1052 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
1053 RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
1054 TransformToType[MVT::ppcf128] = MVT::f64;
1055 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat);
1060 if (!isTypeLegal(MVT::f128)) {
1061 NumRegistersForVT[MVT::f128] = NumRegistersForVT[MVT::i128];
1062 RegisterTypeForVT[MVT::f128] = RegisterTypeForVT[MVT::i128];
1063 TransformToType[MVT::f128] = MVT::i128;
1064 ValueTypeActions.setTypeAction(MVT::f128, TypeSoftenFloat);
1069 if (!isTypeLegal(MVT::f64)) {
1070 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
1071 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
1072 TransformToType[MVT::f64] = MVT::i64;
1073 ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat);
1078 if (!isTypeLegal(MVT::f32)) {
1079 if (isTypeLegal(MVT::f64)) {
1080 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64];
1081 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64];
1082 TransformToType[MVT::f32] = MVT::f64;
1083 ValueTypeActions.setTypeAction(MVT::f32, TypePromoteInteger);
1085 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
1086 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
1087 TransformToType[MVT::f32] = MVT::i32;
1088 ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat);
1093 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
1094 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
1095 MVT VT = (MVT::SimpleValueType) i;
1099 MVT EltVT = VT.getVectorElementType();
1107 for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
1108 MVT SVT = (MVT::SimpleValueType) nVT;
1127 for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
1128 MVT SVT = (MVT::SimpleValueType) nVT;
1144 MVT IntermediateVT;
1145 MVT RegisterVT;
1151 MVT NVT = VT.getPow2VectorType();
1154 TransformToType[i] = MVT::Other;
1175 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
1178 std::tie(RRC, Cost) = findRepresentativeClass((MVT::SimpleValueType)i);
1189 MVT::SimpleValueType TargetLoweringBase::getCmpLibcallReturnType() const {
1190 return MVT::i32; // return the default value
1194 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
1195 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
1196 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
1205 MVT &RegisterVT) const {
1251 MVT DestVT = getRegisterType(Context, NewVT);
1293 MVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32);
1299 MVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT);
1399 std::pair<unsigned, MVT>
