Lines Matching refs:FS
49 StringRef CPU, StringRef FS,
53 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
54 Subtarget(TT, CPU, FS, *this, isLittle, Options) {
74 StringRef FS, const TargetOptions &Options,
77 : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, isLittle) {
87 StringRef CPU, StringRef FS,
91 : ARMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
96 StringRef CPU, StringRef FS,
100 : ARMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
105 StringRef CPU, StringRef FS,
109 : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL,
117 StringRef CPU, StringRef FS,
121 : ThumbTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
126 StringRef CPU, StringRef FS,
130 : ThumbTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
