Lines Matching defs:Vd
1247 unsigned Vd = fieldFromInstruction(Val, 8, 5);
1251 if (regs == 0 || (Vd + regs) > 32) {
1252 regs = Vd + regs > 32 ? 32 - Vd : regs;
1257 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
1260 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1271 unsigned Vd = fieldFromInstruction(Val, 8, 5);
1275 if (regs == 0 || regs > 16 || (Vd + regs) > 32) {
1276 regs = Vd + regs > 32 ? 32 - Vd : regs;
1282 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
1285 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
4880 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
4881 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
4899 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
4910 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
4911 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
4929 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder)))
