Lines Matching defs:Const
139 bool parseMemOffset(const MCExpr *&Res, bool isParenExpr);
140 bool parseRelocOperand(const MCExpr *&Res);
142 const MCExpr *evaluateRelocExpr(const MCExpr *Expr, StringRef RelocStr);
144 bool isEvaluated(const MCExpr *Expr);
227 const MCInstrInfo &MII, const MCTargetOptions &Options)
244 MCAsmParser &getParser() const { return Parser; }
245 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
248 bool hasEightFccRegisters() const { return hasMips4() || hasMips32(); }
250 bool isGP64bit() const { return STI.getFeatureBits() & Mips::FeatureGP64Bit; }
251 bool isFP64bit() const { return STI.getFeatureBits() & Mips::FeatureFP64Bit; }
252 bool isABI_N32() const { return STI.getFeatureBits() & Mips::FeatureN32; }
253 bool isABI_N64() const { return STI.getFeatureBits() & Mips::FeatureN64; }
254 bool isABI_O32() const { return STI.getFeatureBits() & Mips::FeatureO32; }
255 bool isABI_FPXX() const { return false; } // TODO: add check for FeatureXX
257 bool allowOddSPReg() const {
261 bool inMicroMipsMode() const {
264 bool hasMips1() const { return STI.getFeatureBits() & Mips::FeatureMips1; }
265 bool hasMips2() const { return STI.getFeatureBits() & Mips::FeatureMips2; }
266 bool hasMips3() const { return STI.getFeatureBits() & Mips::FeatureMips3; }
267 bool hasMips4() const { return STI.getFeatureBits() & Mips::FeatureMips4; }
268 bool hasMips5() const { return STI.getFeatureBits() & Mips::FeatureMips5; }
269 bool hasMips32() const {
272 bool hasMips64() const {
275 bool hasMips32r2() const {
278 bool hasMips64r2() const {
281 bool hasMips32r6() const {
284 bool hasMips64r6() const {
287 bool hasDSP() const { return (STI.getFeatureBits() & Mips::FeatureDSP); }
288 bool hasDSPR2() const { return (STI.getFeatureBits() & Mips::FeatureDSPR2); }
289 bool hasMSA() const { return (STI.getFeatureBits() & Mips::FeatureMSA); }
291 bool inMips16Mode() const {
295 bool mipsSEUsesSoftFloat() const { return false; }
348 const char *Data;
359 const MCRegisterInfo *RegInfo;
363 const MCExpr *Val;
368 const MCExpr *Off;
383 const MCRegisterInfo *RegInfo,
398 unsigned getGPR32Reg() const {
407 unsigned getGPR64Reg() const {
416 unsigned getAFGR64Reg() const {
426 unsigned getFGR64Reg() const {
434 unsigned getFGR32Reg() const {
442 unsigned getFGRH32Reg() const {
450 unsigned getFCCReg() const {
458 unsigned getMSA128Reg() const {
468 unsigned getMSACtrlReg() const {
476 unsigned getCOP2Reg() const {
484 unsigned getCOP3Reg() const {
492 unsigned getACC64DSPReg() const {
500 unsigned getHI32DSPReg() const {
508 unsigned getLO32DSPReg() const {
516 unsigned getCCRReg() const {
524 unsigned getHWRegsReg() const {
531 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
535 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
541 void addRegOperands(MCInst &Inst, unsigned N) const {
548 void addGPR32AsmRegOperands(MCInst &Inst, unsigned N) const {
556 void addGPR64AsmRegOperands(MCInst &Inst, unsigned N) const {
561 void addAFGR64AsmRegOperands(MCInst &Inst, unsigned N) const {
566 void addFGR64AsmRegOperands(MCInst &Inst, unsigned N) const {
571 void addFGR32AsmRegOperands(MCInst &Inst, unsigned N) const {
580 void addFGRH32AsmRegOperands(MCInst &Inst, unsigned N) const {
585 void addFCCAsmRegOperands(MCInst &Inst, unsigned N) const {
590 void addMSA128AsmRegOperands(MCInst &Inst, unsigned N) const {
595 void addMSACtrlAsmRegOperands(MCInst &Inst, unsigned N) const {
600 void addCOP2AsmRegOperands(MCInst &Inst, unsigned N) const {
605 void addCOP3AsmRegOperands(MCInst &Inst, unsigned N) const {
610 void addACC64DSPAsmRegOperands(MCInst &Inst, unsigned N) const {
615 void addHI32DSPAsmRegOperands(MCInst &Inst, unsigned N) const {
620 void addLO32DSPAsmRegOperands(MCInst &Inst, unsigned N) const {
625 void addCCRAsmRegOperands(MCInst &Inst, unsigned N) const {
630 void addHWRegsAsmRegOperands(MCInst &Inst, unsigned N) const {
635 void addImmOperands(MCInst &Inst, unsigned N) const {
637 const MCExpr *Expr = getImm();
641 void addMemOperands(MCInst &Inst, unsigned N) const {
646 const MCExpr *Expr = getMemOff();
650 bool isReg() const override {
658 bool isRegIdx() const { return Kind == k_RegisterIndex; }
659 bool isImm() const override { return Kind == k_Immediate; }
660 bool isConstantImm() const {
663 bool isToken() const override {
668 bool isMem() const override { return Kind == k_Memory; }
669 bool isConstantMemOff() const {
672 template <unsigned Bits> bool isMemWithSimmOffset() const {
675 bool isInvNum() const { return Kind == k_Immediate; }
676 bool isLSAImm() const {
683 StringRef getToken() const {
688 unsigned getReg() const override {
699 const MCExpr *getImm() const {
704 int64_t getConstantImm() const {
705 const MCExpr *Val = getImm();
706 return static_cast<const MCConstantExpr *>(Val)->getValue();
709 MipsOperand *getMemBase() const {
714 const MCExpr *getMemOff() const {
719 int64_t getConstantMemOff() const {
720 return static_cast<const MCConstantExpr *>(getMemOff())->getValue();
736 CreateNumericReg(unsigned Index, const MCRegisterInfo *RegInfo, SMLoc S,
745 CreateGPRReg(unsigned Index, const MCRegisterInfo *RegInfo, SMLoc S, SMLoc E,
753 CreateFGRReg(unsigned Index, const MCRegisterInfo *RegInfo, SMLoc S, SMLoc E,
761 CreateFCCReg(unsigned Index, const MCRegisterInfo *RegInfo, SMLoc S, SMLoc E,
769 CreateACCReg(unsigned Index, const MCRegisterInfo *RegInfo, SMLoc S, SMLoc E,
777 CreateMSA128Reg(unsigned Index, const MCRegisterInfo *RegInfo, SMLoc S,
785 CreateMSACtrlReg(unsigned Index, const MCRegisterInfo *RegInfo, SMLoc S,
791 CreateImm(const MCExpr *Val, SMLoc S, SMLoc E, MipsAsmParser &Parser) {
800 CreateMem(std::unique_ptr<MipsOperand> Base, const MCExpr *Off, SMLoc S,
810 bool isGPRAsmReg() const {
813 bool isFGRAsmReg() const {
817 bool isHWRegsAsmReg() const {
820 bool isCCRAsmReg() const {
823 bool isFCCAsmReg() const {
830 bool isACCAsmReg() const {
833 bool isCOP2AsmReg() const {
836 bool isCOP3AsmReg() const {
839 bool isMSA128AsmReg() const {
842 bool isMSACtrlAsmReg() const {
847 SMLoc getStartLoc() const override { return StartLoc; }
849 SMLoc getEndLoc() const override { return EndLoc; }
865 void print(raw_ostream &OS) const override {
894 extern const MCInstrDesc MipsInsts[];
896 static const MCInstrDesc &getInstDesc(unsigned Opcode) {
902 const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode());
907 const unsigned Opcode = Inst.getOpcode();
981 const MCOperandInfo &OpInfo = MCID.OpInfo[i];
993 const MCExpr *Expr = Op.getExpr();
995 const MCSymbolRefExpr *SR =
996 static_cast<const MCSymbolRefExpr *>(Expr);
1080 const MCOperand &ImmOp = Inst.getOperand(1);
1082 const MCOperand &RegOp = Inst.getOperand(0);
1178 const MCOperand &ImmOp = Inst.getOperand(2);
1180 const MCOperand &SrcRegOp = Inst.getOperand(1);
1182 const MCOperand &DstRegOp = Inst.getOperand(0);
1222 const MCOperand &ImmOp = Inst.getOperand(1);
1224 const MCOperand &RegOp = Inst.getOperand(0);
1256 const MCSymbolRefExpr *SR;
1259 const MCExpr *ExprOffset;
1302 const MCInstrDesc &Desc = getInstDesc(Inst.getOpcode());
1326 SR = static_cast<const MCSymbolRefExpr *>(ExprOffset);
1327 const MCSymbolRefExpr *HiExpr = MCSymbolRefExpr::Create(
1332 const MCExpr *HiExpr = evaluateRelocExpr(ExprOffset, "hi");
1356 const MCSymbolRefExpr *LoExpr = MCSymbolRefExpr::Create(
1361 const MCExpr *LoExpr = evaluateRelocExpr(ExprOffset, "lo");
1640 const MCExpr *Res =
1659 const MCExpr *IdVal;
1673 const MCExpr *MipsAsmParser::evaluateRelocExpr(const MCExpr *Expr,
1675 const MCExpr *Res;
1677 if (const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(Expr)) {
1704 if (const MCSymbolRefExpr *MSRE = dyn_cast<MCSymbolRefExpr>(Expr)) {
1712 if (const MCBinaryExpr *BE = dyn_cast<MCBinaryExpr>(Expr)) {
1719 const MCExpr *LExp = evaluateRelocExpr(BE->getLHS(), RelocStr);
1720 const MCExpr *RExp = evaluateRelocExpr(BE->getRHS(), RelocStr);
1725 if (const MCUnaryExpr *UN = dyn_cast<MCUnaryExpr>(Expr)) {
1726 const MCExpr *UnExp = evaluateRelocExpr(UN->getSubExpr(), RelocStr);
1734 bool MipsAsmParser::isEvaluated(const MCExpr *Expr) {
1742 if (const MCBinaryExpr *BE = dyn_cast<MCBinaryExpr>(Expr)) {
1755 bool MipsAsmParser::parseRelocOperand(const MCExpr *&Res) {
1757 const AsmToken &Tok = Parser.getTok(); // Get next token, operation.
1765 const MCExpr *IdVal;
1773 const AsmToken &nextTok = Parser.getTok();
1823 bool MipsAsmParser::parseMemOffset(const MCExpr *&Res, bool isParenExpr) {
1854 const MCExpr *IdVal = nullptr;
1870 const AsmToken &Tok = Parser.getTok(); // Get the next token.
1921 if (const MCBinaryExpr *BE = dyn_cast<MCBinaryExpr>(IdVal)) {
1939 const MCExpr *Expr;
1945 const MCSymbolRefExpr *Ref = static_cast<const MCSymbolRefExpr *>(Expr);
1946 const StringRef DefSymbol = Ref->getSymbol().getName();
1959 const MCConstantExpr *Const = static_cast<const MCConstantExpr *>(Expr);
1961 MipsOperand::CreateImm(Const, S, Parser.getTok().getLoc(), *this));
2081 const MCExpr *IdVal;
2107 const MCExpr *Expr = nullptr;
2119 const MCExpr *IdVal;
2126 const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(IdVal);
2147 const MCExpr *Expr;
2359 const AsmToken &Reg = Parser.getTok();
2486 const MCExpr *Value;
2604 const AsmToken &Tok = Parser.getTok();
2638 const AsmToken &Tok = Parser.getTok();
2659 const AsmToken &Tok = Parser.getTok();
2707 const MCExpr *Value;
2730 const MCExpr *Value;
2746 const MCExpr *Value;
