Lines Matching refs:Low
430 // (low) operations are left as Legal, as there are single-result
432 // when both high and low results are needed must be arranged by dagcombine.
3668 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3669 return (Val < 0) || (Val >= Low && Val < Hi);
3682 unsigned Pos, unsigned Size, int Low) {
3683 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3684 if (!isUndefOrEqual(Mask[i], Low))
4382 /// to the same elements of the low, but to the higher half of the source.
5083 // into the low and high part. This is necessary because we want
5093 /// vector of zero or undef vector. This produces a shuffle where the low
5106 // If this is the insertion idx, put the low elt of V2 here.
5685 // consecutive loads for the low half, generate a vzext_load node.
6586 // Now we have our 32-bit value zero extended in the low element of
6600 // If we have a constant or non-constant insertion into the low element of
6650 // is a non-constant being inserted into an element other than the low one,
6652 // movd/movss) to move this into the low element, then shuffle it into
6795 // For SSE 4.1, use insertps to put the high elements into the low element.
7057 // the low bit.
7076 // high or low half formed.
7088 // Handle the easy case where we have V1 in the low lanes and V2 in the
7093 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
7199 // Before we had 3-1 in the low half and 3-1 in the high half. Afterward, 2-2
7241 // At this point there are at most two inputs to the low and high halves from
7244 // We use at most one low and one high word shuffle to collect these paired
7269 // a dword. We find the adjacent index by toggling the low bit.
7413 "Failed to lift all the high half inputs to the low mask!");
7416 "Failed to lift all the low half inputs to the high mask!");
7418 // Do a half shuffle for the low mask.
7527 // If the low inputs are spread across two dwords, pack them into
7536 // Otherwise pin the low inputs.
7594 /// the two inputs, try to interleave them. Otherwise, blend the low and high
7633 // FIXME: Figure out whether we should pack these into the low or high
7739 // there are two adjacent bytes after we move the low one.
7789 // FIXME: Figure out whether we should pack these into the low or high
7854 // Otherwise just unpack the low half of V into V1 and the high half into
7957 // low and high halves of AVX 256-bit vectors.
7988 // number of uses of V2 in the low half of the vector.
8156 // Determine if more than 1 of the words in each of the low and high quadwords
8305 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
8608 /// getVZextMovL - Return a zero-extending vector move low node.
9422 // Shuffling low element of v1 into undef, just return v1.
12334 // Create masks for only the low parts/high parts of the 64 bit integers.
14298 // The EAX register is loaded with the low-order 32 bits. The EDX register
14326 // and the EAX register is loaded with the low-order 32 bits.
14353 // the EAX register is loaded with the low-order 32 bits.
15328 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
15489 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18298 /// inserting the result into the low part of a new 256-bit vector
18313 /// same as extracting the low 128-bit part of 256-bit vector and then
18479 // Check that the low words (being shuffled) are the identity in the
18489 // dword shuffle, and the low words are self-contained.
