Lines Matching refs:RegBank
61 void EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank,
63 void emitComposeSubRegIndices(raw_ostream &OS, CodeGenRegBank &RegBank,
160 EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank,
162 unsigned NumRCs = RegBank.getRegClasses().size();
163 unsigned NumSets = RegBank.getNumRegPressureSets();
170 const CodeGenRegisterClass &RC = *RegBank.getRegClasses()[i];
177 OS << " {" << (*Regs.begin())->getWeight(RegBank)
178 << ", " << RegBank.getRegUnitSetWeight(RegUnits);
189 for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits();
191 if (RegBank.getRegUnit(UnitIdx).Weight > 1)
197 << " assert(RegUnit < " << RegBank.getNumNativeRegUnits()
201 for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits();
203 const RegUnit &RU = RegBank.getRegUnit(UnitIdx);
226 OS << " \"" << RegBank.getRegSetAt(i).Name << "\",\n";
238 const RegUnitSet &RegUnits = RegBank.getRegSetAt(i);
248 unsigned NumRCUnitSets = RegBank.getNumRegClassPressureSetLists();
254 ArrayRef<unsigned> PSetIDs = RegBank.getRCPressureSetIDs(i);
259 PSets.push_back(RegBank.getRegPressureSet(*PSetI).Order);
268 OS << RegBank.getRegClasses()[i]->getName();
273 OS << "~" << RegBank.getRegSetAt(*PSetI).Name;
300 << " assert(RegUnit < " << RegBank.getNumNativeRegUnits()
303 for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits();
305 OS << RCSetStarts[RegBank.getRegUnit(UnitIdx).RegClassUnitSetsIdx] << ",";
631 CodeGenRegBank &RegBank,
633 ArrayRef<CodeGenSubRegIndex*> SubRegIndices = RegBank.getSubRegIndices();
702 CodeGenRegBank &RegBank) {
708 const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters();
710 ArrayRef<CodeGenSubRegIndex*> SubRegIndices = RegBank.getSubRegIndices();
738 Reg->addSubRegsPreOrder(SR, RegBank);
835 for (unsigned i = 0, e = RegBank.getNumNativeRegUnits(); i != e; ++i) {
836 ArrayRef<const CodeGenRegister*> Roots = RegBank.getRegUnit(i).getRoots();
846 ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses();
934 << RegBank.getNumNativeRegUnits() << ", "
952 CodeGenRegBank &RegBank) {
970 if (!RegBank.getSubRegIndices().empty()) {
988 ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses();
1012 CodeGenRegBank &RegBank){
1025 ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses();
1026 ArrayRef<CodeGenSubRegIndex*> SubRegIndices = RegBank.getSubRegIndices();
1215 const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters();
1228 emitComposeSubRegIndices(OS, RegBank, ClassName);
1264 EmitRegUnitPressure(OS, RegBank, ClassName);
1283 OS.write_hex(RegBank.CoveringLanes);
1289 << " " << RegBank.getNumNativeRegUnits() << ",\n"
1307 const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet);
1318 BitVector Covered = RegBank.computeCoveredRegisters(*Regs);
1325 RegBank.getSets().evaluate(OPDag, OPSet, CSRSet->getLoc());
1326 Covered |= RegBank.computeCoveredRegisters(
1343 CodeGenRegBank &RegBank = Target.getRegBank();
1344 RegBank.computeDerivedInfo();
1346 runEnums(OS, Target, RegBank);
1347 runMCDesc(OS, Target, RegBank);
1348 runTargetHeader(OS, Target, RegBank);
1349 runTargetDesc(OS, Target, RegBank);
