Lines Matching refs:cs
152 p = ctx->ws->buffer_map(shader->shader_code_bo->cs_buf, ctx->cs,
217 shader->kernel_param->cs_buf, ctx->cs, PIPE_TRANSFER_WRITE);
257 struct radeon_winsys_cs *cs = rctx->cs;
282 /* XXX: Partition the LDS between PS/CS. By default half (4096 dwords
290 r600_write_config_reg(cs, R_008970_VGT_NUM_INDICES, group_size);
292 r600_write_config_reg_seq(cs, R_00899C_VGT_COMPUTE_START_X, 3);
293 r600_write_value(cs, 0); /* R_00899C_VGT_COMPUTE_START_X */
294 r600_write_value(cs, 0); /* R_0089A0_VGT_COMPUTE_START_Y */
295 r600_write_value(cs, 0); /* R_0089A4_VGT_COMPUTE_START_Z */
297 r600_write_config_reg(cs, R_0089AC_VGT_COMPUTE_THREAD_GROUP_SIZE,
300 r600_write_compute_context_reg_seq(cs, R_0286EC_SPI_COMPUTE_NUM_THREAD_X, 3);
301 r600_write_value(cs, block_layout[0]); /* R_0286EC_SPI_COMPUTE_NUM_THREAD_X */
302 r600_write_value(cs, block_layout[1]); /* R_0286F0_SPI_COMPUTE_NUM_THREAD_Y */
303 r600_write_value(cs, block_layout[2]); /* R_0286F4_SPI_COMPUTE_NUM_THREAD_Z */
305 r600_write_compute_context_reg(cs, CM_R_0288E8_SQ_LDS_ALLOC,
309 r600_write_value(cs, PKT3C(PKT3_DISPATCH_DIRECT, 3, 0));
310 r600_write_value(cs, grid_layout[0]);
311 r600_write_value(cs, grid_layout[1]);
312 r600_write_value(cs, grid_layout[2]);
314 r600_write_value(cs, 1);
320 struct radeon_winsys_cs *cs = ctx->cs;
340 r600_write_compute_context_reg(cs, R_028238_CB_TARGET_MASK,
354 COMPUTE_DBG("resnum: %i, cdw: %i\n", i, cs->cdw);
364 cs->buf[cs->cdw++] = resources[i].cs[j];
398 COMPUTE_DBG("cdw: %i\n", cs->cdw);
399 for (i = 0; i < cs->cdw; i++) {
400 COMPUTE_DBG("%4i : 0x%08X\n", i, ctx->cs->buf[i]);
404 ctx->ws->cs_flush(ctx->cs, RADEON_FLUSH_ASYNC | RADEON_FLUSH_COMPUTE);
431 struct radeon_winsys_cs *cs = rctx->cs;
436 r600_write_compute_context_reg_seq(cs, R_0288D0_SQ_PGM_START_LS, 3);
437 r600_write_value(cs, va >> 8); /* R_0288D0_SQ_PGM_START_LS */
438 r600_write_value(cs, /* R_0288D4_SQ_PGM_RESOURCES_LS */
441 r600_write_value(cs, 0); /* R_0288D8_SQ_PGM_RESOURCES_LS_2 */
443 r600_write_value(cs, PKT3C(PKT3_NOP, 0, 0));
444 r600_write_value(cs, r600_context_bo_reloc(rctx, shader->shader_code_bo,
667 * Set the number of threads used by the CS (aka LS) stage to
682 * set it to the maximum value for the CS (aka LS) stage. */
820 ctx->cs, transfer->usage))) {
