Lines Matching refs:rstate
688 struct r600_pipe_state *rstate;
697 rstate = &blend->rstate;
699 rstate->id = R600_PIPE_STATE_BLEND;
724 r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
756 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl[i]);
759 r600_pipe_state_add_reg(rstate, R_028B70_DB_ALPHA_TO_MASK,
767 return rstate;
783 struct r600_pipe_state *rstate;
794 rstate = &dsa->rstate;
796 rstate->id = R600_PIPE_STATE_DSA;
830 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control);
831 return rstate;
839 struct r600_pipe_state *rstate;
854 rstate = &rs->rstate;
873 rstate->id = R600_PIPE_STATE_RASTERIZER;
885 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp);
889 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
900 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX,
905 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
906 r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MODE_CNTL_0,
912 r600_pipe_state_add_reg(rstate, CM_R_028BE4_PA_SU_VTX_CNTL,
916 r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
920 r600_pipe_state_add_reg(rstate, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
921 r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
932 r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, S_028350_MULTIPASS(state->rasterizer_discard));
933 return rstate;
1135 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1138 if (rstate == NULL)
1142 rstate->id = R600_PIPE_STATE_CLIP;
1144 r600_pipe_state_add_reg(rstate,
1147 r600_pipe_state_add_reg(rstate,
1150 r600_pipe_state_add_reg(rstate,
1153 r600_pipe_state_add_reg(rstate,
1159 rctx->states[R600_PIPE_STATE_CLIP] = rstate;
1160 r600_context_pipe_state_set(rctx, rstate);
1199 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1202 if (rstate == NULL)
1207 rstate->id = R600_PIPE_STATE_SCISSOR;
1208 r600_pipe_state_add_reg(rstate, R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl);
1209 r600_pipe_state_add_reg(rstate, R_028254_PA_SC_VPORT_SCISSOR_0_BR, br);
1212 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
1213 r600_context_pipe_state_set(rctx, rstate);
1220 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1222 if (rstate == NULL)
1226 rstate->id = R600_PIPE_STATE_VIEWPORT;
1227 r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]));
1228 r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]));
1229 r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]));
1230 r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]));
1231 r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]));
1232 r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]));
1235 rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
1236 r600_context_pipe_state_set(rctx, rstate);
1528 static uint32_t evergreen_set_ms_pos(struct pipe_context *ctx, struct r600_pipe_state *rstate, int nsample)
1566 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0 + i*4,
1572 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0 + i*4,
1578 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0 + i*4,
1588 static uint32_t cayman_set_ms_pos(struct pipe_context *ctx, struct r600_pipe_state *rstate, int nsample)
1669 r600_pipe_state_add_reg(rstate, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs[0]);
1670 r600_pipe_state_add_reg(rstate, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs[1]);
1671 r600_pipe_state_add_reg(rstate, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs[2]);
1672 r600_pipe_state_add_reg(rstate, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs[3]);
1674 r600_pipe_state_add_reg(rstate, CM_R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, sample_locs[4]);
1675 r600_pipe_state_add_reg(rstate, CM_R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, sample_locs[5]);
1676 r600_pipe_state_add_reg(rstate, CM_R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, sample_locs[6]);
1677 r600_pipe_state_add_reg(rstate, CM_R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, sample_locs[7]);
1680 r600_pipe_state_add_reg(rstate, CM_R_028C00_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2, sample_locs[8]);
1681 r600_pipe_state_add_reg(rstate, CM_R_028C10_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2, sample_locs[9]);
1682 r600_pipe_state_add_reg(rstate, CM_R_028C20_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2, sample_locs[10]);
1683 r600_pipe_state_add_reg(rstate, CM_R_028C30_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2, sample_locs[11]);
1684 r600_pipe_state_add_reg(rstate, CM_R_028C04_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3, sample_locs[12]);
1685 r600_pipe_state_add_reg(rstate, CM_R_028C14_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3, sample_locs[13]);
1686 r600_pipe_state_add_reg(rstate, CM_R_028C24_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3, sample_locs[14]);
1687 r600_pipe_state_add_reg(rstate, CM_R_028C34_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3, sample_locs[15]);
1696 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1702 if (rstate == NULL)
1708 rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
1734 r600_pipe_state_add_reg_bo(rstate, R_028C60_CB_COLOR0_BASE + i * 0x3C,
1736 r600_pipe_state_add_reg(rstate, R_028C78_CB_COLOR0_DIM + i * 0x3C,
1738 r600_pipe_state_add_reg_bo(rstate, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1740 r600_pipe_state_add_reg(rstate, R_028C64_CB_COLOR0_PITCH + i * 0x3C,
1742 r600_pipe_state_add_reg(rstate, R_028C68_CB_COLOR0_SLICE + i * 0x3C,
1744 r600_pipe_state_add_reg(rstate, R_028C6C_CB_COLOR0_VIEW + i * 0x3C,
1746 r600_pipe_state_add_reg_bo(rstate, R_028C74_CB_COLOR0_ATTRIB + i * 0x3C,
1748 r600_pipe_state_add_reg_bo(rstate, R_028C7C_CB_COLOR0_CMASK + i * 0x3c,
1750 r600_pipe_state_add_reg(rstate, R_028C80_CB_COLOR0_CMASK_SLICE + i * 0x3c,
1752 r600_pipe_state_add_reg_bo(rstate, R_028C84_CB_COLOR0_FMASK + i * 0x3c,
1754 r600_pipe_state_add_reg(rstate, R_028C88_CB_COLOR0_FMASK_SLICE + i * 0x3c,
1765 r600_pipe_state_add_reg_bo(rstate, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
1770 r600_pipe_state_add_reg(rstate, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
1798 r600_pipe_state_add_reg_bo(rstate, R_028048_DB_Z_READ_BASE, surf->db_depth_base,
1800 r600_pipe_state_add_reg_bo(rstate, R_028050_DB_Z_WRITE_BASE, surf->db_depth_base,
1802 r600_pipe_state_add_reg(rstate, R_028008_DB_DEPTH_VIEW, surf->db_depth_view);
1804 r600_pipe_state_add_reg_bo(rstate, R_02804C_DB_STENCIL_READ_BASE, surf->db_stencil_base,
1806 r600_pipe_state_add_reg_bo(rstate, R_028054_DB_STENCIL_WRITE_BASE, surf->db_stencil_base,
1808 r600_pipe_state_add_reg_bo(rstate, R_028044_DB_STENCIL_INFO, surf->db_stencil_info,
1811 r600_pipe_state_add_reg_bo(rstate, R_028040_DB_Z_INFO, surf->db_depth_info,
1813 r600_pipe_state_add_reg(rstate, R_028058_DB_DEPTH_SIZE, surf->db_depth_size);
1814 r600_pipe_state_add_reg(rstate, R_02805C_DB_DEPTH_SLICE, surf->db_depth_slice);
1820 r600_pipe_state_add_reg(rstate,
1822 r600_pipe_state_add_reg(rstate,
1839 unsigned max_dist = cayman_set_ms_pos(ctx, rstate, nr_samples);
1841 r600_pipe_state_add_reg(rstate, CM_R_028BDC_PA_SC_LINE_CNTL, line_cntl);
1842 r600_pipe_state_add_reg(rstate, CM_R_028BE0_PA_SC_AA_CONFIG,
1846 r600_pipe_state_add_reg(rstate, CM_R_028804_DB_EQAA,
1854 unsigned max_dist = evergreen_set_ms_pos(ctx, rstate, nr_samples);
1856 r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, line_cntl);
1857 r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG,
1865 r600_pipe_state_add_reg(rstate, CM_R_028BDC_PA_SC_LINE_CNTL, S_028C00_LAST_PIXEL(1));
1866 r600_pipe_state_add_reg(rstate, CM_R_028BE0_PA_SC_AA_CONFIG, 0);
1867 r600_pipe_state_add_reg(rstate, CM_R_028804_DB_EQAA,
1872 r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, S_028C00_LAST_PIXEL(1));
1873 r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG, 0);
1878 rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
1879 r600_context_pipe_state_set(rctx, rstate);
2970 struct r600_pipe_state *rstate = &shader->rstate;
2979 rstate->nregs = 0;
3017 r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + idx * 4,
3084 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0,
3086 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1,
3088 r600_pipe_state_add_reg(rstate, R_0286E4_SPI_PS_IN_CONTROL_2,
3090 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z);
3091 r600_pipe_state_add_reg(rstate,
3095 r600_pipe_state_add_reg_bo(rstate,
3099 r600_pipe_state_add_reg(rstate,
3104 r600_pipe_state_add_reg(rstate,
3119 struct r600_pipe_state *rstate = &shader->rstate;
3125 rstate->nregs = 0;
3136 r600_pipe_state_add_reg(rstate,
3148 r600_pipe_state_add_reg(rstate,
3151 r600_pipe_state_add_reg(rstate,
3155 r600_pipe_state_add_reg_bo(rstate,
3171 struct r600_pipe_state *rstate = &ve->rstate;
3172 rstate->id = R600_PIPE_STATE_FETCH_SHADER;
3173 rstate->nregs = 0;
3174 r600_pipe_state_add_reg_bo(rstate, R_0288A4_SQ_PGM_START_FS,
3182 struct r600_pipe_state *rstate;
3187 rstate = evergreen_create_blend_state_mode(&rctx->context, &blend, V_028808_CB_RESOLVE);
3188 return rstate;
3194 struct r600_pipe_state *rstate;
3199 rstate = evergreen_create_blend_state_mode(&rctx->context, &blend, V_028808_CB_DECOMPRESS);
3200 return rstate;
3224 struct r600_pipe_state rstate;
3228 rstate.nregs = 0;
3229 r600_pipe_state_add_reg(&rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control);
3230 r600_context_pipe_state_set(rctx, &rstate);
