Lines Matching refs:cs
1758 struct radeon_winsys_cs *cs = rctx->cs;
1762 r600_write_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1764 r600_write_value(cs, 0xff); /* R_028238_CB_TARGET_MASK */
1765 r600_write_value(cs, 0xff); /* R_02823C_CB_SHADER_MASK */
1767 r600_write_value(cs, 0xf); /* R_028238_CB_TARGET_MASK */
1768 r600_write_value(cs, 0xf); /* R_02823C_CB_SHADER_MASK */
1770 r600_write_context_reg(cs, R_028808_CB_COLOR_CONTROL, a->cb_color_control);
1776 r600_write_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1777 r600_write_value(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */
1779 r600_write_value(cs, 0xf | (multiwrite ? fb_colormask : ps_colormask)); /* R_02823C_CB_SHADER_MASK */
1780 r600_write_context_reg(cs, R_028808_CB_COLOR_CONTROL,
1788 struct radeon_winsys_cs *cs = rctx->cs;
1811 r600_write_context_reg_seq(cs, R_028D0C_DB_RENDER_CONTROL, 2);
1812 r600_write_value(cs, db_render_control); /* R_028D0C_DB_RENDER_CONTROL */
1813 r600_write_value(cs, db_render_override); /* R_028D10_DB_RENDER_OVERRIDE */
1818 struct radeon_winsys_cs *cs = rctx->cs;
1834 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1835 r600_write_value(cs, (320 + buffer_index) * 7);
1836 r600_write_value(cs, offset); /* RESOURCEi_WORD0 */
1837 r600_write_value(cs, rbuffer->buf->size - offset - 1); /* RESOURCEi_WORD1 */
1838 r600_write_value(cs, /* RESOURCEi_WORD2 */
1841 r600_write_value(cs, 0); /* RESOURCEi_WORD3 */
1842 r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
1843 r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
1844 r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD6 */
1846 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1847 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1857 struct radeon_winsys_cs *cs = rctx->cs;
1872 r600_write_context_reg(cs, reg_alu_constbuf_size + buffer_index * 4,
1874 r600_write_context_reg(cs, reg_alu_const_cache + buffer_index * 4, offset >> 8);
1876 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1877 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1879 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1880 r600_write_value(cs, (buffer_id_base + buffer_index) * 7);
1881 r600_write_value(cs, offset); /* RESOURCEi_WORD0 */
1882 r600_write_value(cs, rbuffer->buf->size - offset - 1); /* RESOURCEi_WORD1 */
1883 r600_write_value(cs, /* RESOURCEi_WORD2 */
1886 r600_write_value(cs, 0); /* RESOURCEi_WORD3 */
1887 r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
1888 r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
1889 r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD6 */
1891 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1892 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1917 struct radeon_winsys_cs *cs = rctx->cs;
1928 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1929 r600_write_value(cs, (resource_id_base + resource_index) * 7);
1930 r600_write_array(cs, 7, rview->tex_resource_words);
1935 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1936 r600_write_value(cs, reloc);
1937 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1938 r600_write_value(cs, reloc);
1958 struct radeon_winsys_cs *cs = rctx->cs;
1982 r600_write_value(cs, PKT3(PKT3_SET_SAMPLER, 3, 0));
1983 r600_write_value(cs, (resource_id_base + i) * 3);
1984 r600_write_array(cs, 3, texinfo->samplers[i]->tex_sampler_words);
1991 r600_write_config_reg_seq(cs, offset, 4);
1992 r600_write_array(cs, 4, texinfo->samplers[i]->border_color);
2009 struct radeon_winsys_cs *cs = rctx->cs;
2019 r600_write_config_reg(cs, R_009508_TA_CNTL_AUX, tmp);
2027 r600_write_context_reg(rctx->cs, R_028C48_PA_SC_AA_MASK,
