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      1 //===-- ARMBaseInfo.h - Top level definitions for ARM -------- --*- C++ -*-===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file contains small standalone helper functions and enum definitions for
     11 // the ARM target useful for the compiler back-end and the MC libraries.
     12 // As such, it deliberately does not include references to LLVM core
     13 // code gen types, passes, etc..
     14 //
     15 //===----------------------------------------------------------------------===//
     16 
     17 #ifndef ARMBASEINFO_H
     18 #define ARMBASEINFO_H
     19 
     20 #include "ARMMCTargetDesc.h"
     21 #include "llvm/Support/ErrorHandling.h"
     22 
     23 namespace llvm {
     24 
     25 // Enums corresponding to ARM condition codes
     26 namespace ARMCC {
     27   // The CondCodes constants map directly to the 4-bit encoding of the
     28   // condition field for predicated instructions.
     29   enum CondCodes { // Meaning (integer)          Meaning (floating-point)
     30     EQ,            // Equal                      Equal
     31     NE,            // Not equal                  Not equal, or unordered
     32     HS,            // Carry set                  >, ==, or unordered
     33     LO,            // Carry clear                Less than
     34     MI,            // Minus, negative            Less than
     35     PL,            // Plus, positive or zero     >, ==, or unordered
     36     VS,            // Overflow                   Unordered
     37     VC,            // No overflow                Not unordered
     38     HI,            // Unsigned higher            Greater than, or unordered
     39     LS,            // Unsigned lower or same     Less than or equal
     40     GE,            // Greater than or equal      Greater than or equal
     41     LT,            // Less than                  Less than, or unordered
     42     GT,            // Greater than               Greater than
     43     LE,            // Less than or equal         <, ==, or unordered
     44     AL             // Always (unconditional)     Always (unconditional)
     45   };
     46 
     47   inline static CondCodes getOppositeCondition(CondCodes CC) {
     48     switch (CC) {
     49     default: llvm_unreachable("Unknown condition code");
     50     case EQ: return NE;
     51     case NE: return EQ;
     52     case HS: return LO;
     53     case LO: return HS;
     54     case MI: return PL;
     55     case PL: return MI;
     56     case VS: return VC;
     57     case VC: return VS;
     58     case HI: return LS;
     59     case LS: return HI;
     60     case GE: return LT;
     61     case LT: return GE;
     62     case GT: return LE;
     63     case LE: return GT;
     64     }
     65   }
     66 } // namespace ARMCC
     67 
     68 inline static const char *ARMCondCodeToString(ARMCC::CondCodes CC) {
     69   switch (CC) {
     70   case ARMCC::EQ:  return "eq";
     71   case ARMCC::NE:  return "ne";
     72   case ARMCC::HS:  return "hs";
     73   case ARMCC::LO:  return "lo";
     74   case ARMCC::MI:  return "mi";
     75   case ARMCC::PL:  return "pl";
     76   case ARMCC::VS:  return "vs";
     77   case ARMCC::VC:  return "vc";
     78   case ARMCC::HI:  return "hi";
     79   case ARMCC::LS:  return "ls";
     80   case ARMCC::GE:  return "ge";
     81   case ARMCC::LT:  return "lt";
     82   case ARMCC::GT:  return "gt";
     83   case ARMCC::LE:  return "le";
     84   case ARMCC::AL:  return "al";
     85   }
     86   llvm_unreachable("Unknown condition code");
     87 }
     88 
     89 namespace ARM_PROC {
     90   enum IMod {
     91     IE = 2,
     92     ID = 3
     93   };
     94 
     95   enum IFlags {
     96     F = 1,
     97     I = 2,
     98     A = 4
     99   };
    100 
    101   inline static const char *IFlagsToString(unsigned val) {
    102     switch (val) {
    103     default: llvm_unreachable("Unknown iflags operand");
    104     case F: return "f";
    105     case I: return "i";
    106     case A: return "a";
    107     }
    108   }
    109 
    110   inline static const char *IModToString(unsigned val) {
    111     switch (val) {
    112     default: llvm_unreachable("Unknown imod operand");
    113     case IE: return "ie";
    114     case ID: return "id";
    115     }
    116   }
    117 }
    118 
    119 namespace ARM_MB {
    120   // The Memory Barrier Option constants map directly to the 4-bit encoding of
    121   // the option field for memory barrier operations.
    122   enum MemBOpt {
    123     RESERVED_0 = 0,
    124     OSHLD = 1,
    125     OSHST = 2,
    126     OSH   = 3,
    127     RESERVED_4 = 4,
    128     NSHLD = 5,
    129     NSHST = 6,
    130     NSH   = 7,
    131     RESERVED_8 = 8,
    132     ISHLD = 9,
    133     ISHST = 10,
    134     ISH   = 11,
    135     RESERVED_12 = 12,
    136     LD = 13,
    137     ST    = 14,
    138     SY    = 15
    139   };
    140 
    141   inline static const char *MemBOptToString(unsigned val, bool HasV8) {
    142     switch (val) {
    143     default: llvm_unreachable("Unknown memory operation");
    144     case SY:    return "sy";
    145     case ST:    return "st";
    146     case LD: return HasV8 ? "ld" : "#0xd";
    147     case RESERVED_12: return "#0xc";
    148     case ISH:   return "ish";
    149     case ISHST: return "ishst";
    150     case ISHLD: return HasV8 ?  "ishld" : "#0x9";
    151     case RESERVED_8: return "#0x8";
    152     case NSH:   return "nsh";
    153     case NSHST: return "nshst";
    154     case NSHLD: return HasV8 ? "nshld" : "#0x5";
    155     case RESERVED_4: return "#0x4";
    156     case OSH:   return "osh";
    157     case OSHST: return "oshst";
    158     case OSHLD: return HasV8 ? "oshld" : "#0x1";
    159     case RESERVED_0: return "#0x0";
    160     }
    161   }
    162 } // namespace ARM_MB
    163 
    164 namespace ARM_ISB {
    165   enum InstSyncBOpt {
    166     RESERVED_0 = 0,
    167     RESERVED_1 = 1,
    168     RESERVED_2 = 2,
    169     RESERVED_3 = 3,
    170     RESERVED_4 = 4,
    171     RESERVED_5 = 5,
    172     RESERVED_6 = 6,
    173     RESERVED_7 = 7,
    174     RESERVED_8 = 8,
    175     RESERVED_9 = 9,
    176     RESERVED_10 = 10,
    177     RESERVED_11 = 11,
    178     RESERVED_12 = 12,
    179     RESERVED_13 = 13,
    180     RESERVED_14 = 14,
    181     SY = 15
    182   };
    183 
    184   inline static const char *InstSyncBOptToString(unsigned val) {
    185     switch (val) {
    186     default:
    187       llvm_unreachable("Unknown memory operation");
    188       case RESERVED_0:  return "#0x0";
    189       case RESERVED_1:  return "#0x1";
    190       case RESERVED_2:  return "#0x2";
    191       case RESERVED_3:  return "#0x3";
    192       case RESERVED_4:  return "#0x4";
    193       case RESERVED_5:  return "#0x5";
    194       case RESERVED_6:  return "#0x6";
    195       case RESERVED_7:  return "#0x7";
    196       case RESERVED_8:  return "#0x8";
    197       case RESERVED_9:  return "#0x9";
    198       case RESERVED_10: return "#0xa";
    199       case RESERVED_11: return "#0xb";
    200       case RESERVED_12: return "#0xc";
    201       case RESERVED_13: return "#0xd";
    202       case RESERVED_14: return "#0xe";
    203       case SY:          return "sy";
    204     }
    205   }
    206 } // namespace ARM_ISB
    207 
    208 /// isARMLowRegister - Returns true if the register is a low register (r0-r7).
    209 ///
    210 static inline bool isARMLowRegister(unsigned Reg) {
    211   using namespace ARM;
    212   switch (Reg) {
    213   case R0:  case R1:  case R2:  case R3:
    214   case R4:  case R5:  case R6:  case R7:
    215     return true;
    216   default:
    217     return false;
    218   }
    219 }
    220 
    221 /// ARMII - This namespace holds all of the target specific flags that
    222 /// instruction info tracks.
    223 ///
    224 namespace ARMII {
    225 
    226   /// ARM Index Modes
    227   enum IndexMode {
    228     IndexModeNone  = 0,
    229     IndexModePre   = 1,
    230     IndexModePost  = 2,
    231     IndexModeUpd   = 3
    232   };
    233 
    234   /// ARM Addressing Modes
    235   enum AddrMode {
    236     AddrModeNone    = 0,
    237     AddrMode1       = 1,
    238     AddrMode2       = 2,
    239     AddrMode3       = 3,
    240     AddrMode4       = 4,
    241     AddrMode5       = 5,
    242     AddrMode6       = 6,
    243     AddrModeT1_1    = 7,
    244     AddrModeT1_2    = 8,
    245     AddrModeT1_4    = 9,
    246     AddrModeT1_s    = 10, // i8 * 4 for pc and sp relative data
    247     AddrModeT2_i12  = 11,
    248     AddrModeT2_i8   = 12,
    249     AddrModeT2_so   = 13,
    250     AddrModeT2_pc   = 14, // +/- i12 for pc relative data
    251     AddrModeT2_i8s4 = 15, // i8 * 4
    252     AddrMode_i12    = 16
    253   };
    254 
    255   inline static const char *AddrModeToString(AddrMode addrmode) {
    256     switch (addrmode) {
    257     case AddrModeNone:    return "AddrModeNone";
    258     case AddrMode1:       return "AddrMode1";
    259     case AddrMode2:       return "AddrMode2";
    260     case AddrMode3:       return "AddrMode3";
    261     case AddrMode4:       return "AddrMode4";
    262     case AddrMode5:       return "AddrMode5";
    263     case AddrMode6:       return "AddrMode6";
    264     case AddrModeT1_1:    return "AddrModeT1_1";
    265     case AddrModeT1_2:    return "AddrModeT1_2";
    266     case AddrModeT1_4:    return "AddrModeT1_4";
    267     case AddrModeT1_s:    return "AddrModeT1_s";
    268     case AddrModeT2_i12:  return "AddrModeT2_i12";
    269     case AddrModeT2_i8:   return "AddrModeT2_i8";
    270     case AddrModeT2_so:   return "AddrModeT2_so";
    271     case AddrModeT2_pc:   return "AddrModeT2_pc";
    272     case AddrModeT2_i8s4: return "AddrModeT2_i8s4";
    273     case AddrMode_i12:    return "AddrMode_i12";
    274     }
    275   }
    276 
    277   /// Target Operand Flag enum.
    278   enum TOF {
    279     //===------------------------------------------------------------------===//
    280     // ARM Specific MachineOperand flags.
    281 
    282     MO_NO_FLAG = 0,
    283 
    284     /// MO_LO16 - On a symbol operand, this represents a relocation containing
    285     /// lower 16 bit of the address. Used only via movw instruction.
    286     MO_LO16 = 0x1,
    287 
    288     /// MO_HI16 - On a symbol operand, this represents a relocation containing
    289     /// higher 16 bit of the address. Used only via movt instruction.
    290     MO_HI16 = 0x2,
    291 
    292     /// MO_PLT - On a symbol operand, this represents an ELF PLT reference on a
    293     /// call operand.
    294     MO_PLT = 0x3,
    295 
    296     /// MO_OPTION_MASK - Most flags are mutually exclusive; this mask selects
    297     /// just that part of the flag set.
    298     MO_OPTION_MASK = 0x3f,
    299 
    300     /// MO_DLLIMPORT - On a symbol operand, this represents that the reference
    301     /// to the symbol is for an import stub.  This is used for DLL import
    302     /// storage class indication on Windows.
    303     MO_DLLIMPORT = 0x40,
    304 
    305     /// MO_NONLAZY - This is an independent flag, on a symbol operand "FOO" it
    306     /// represents a symbol which, if indirect, will get special Darwin mangling
    307     /// as a non-lazy-ptr indirect symbol (i.e. "L_FOO$non_lazy_ptr"). Can be
    308     /// combined with MO_LO16, MO_HI16 or MO_NO_FLAG (in a constant-pool, for
    309     /// example).
    310     MO_NONLAZY = 0x80,
    311 
    312     // It's undefined behaviour if an enum overflows the range between its
    313     // smallest and largest values, but since these are |ed together, it can
    314     // happen. Put a sentinel in (values of this enum are stored as "unsigned
    315     // char").
    316     MO_UNUSED_MAXIMUM = 0xff
    317   };
    318 
    319   enum {
    320     //===------------------------------------------------------------------===//
    321     // Instruction Flags.
    322 
    323     //===------------------------------------------------------------------===//
    324     // This four-bit field describes the addressing mode used.
    325     AddrModeMask  = 0x1f, // The AddrMode enums are declared in ARMBaseInfo.h
    326 
    327     // IndexMode - Unindex, pre-indexed, or post-indexed are valid for load
    328     // and store ops only.  Generic "updating" flag is used for ld/st multiple.
    329     // The index mode enums are declared in ARMBaseInfo.h
    330     IndexModeShift = 5,
    331     IndexModeMask  = 3 << IndexModeShift,
    332 
    333     //===------------------------------------------------------------------===//
    334     // Instruction encoding formats.
    335     //
    336     FormShift     = 7,
    337     FormMask      = 0x3f << FormShift,
    338 
    339     // Pseudo instructions
    340     Pseudo        = 0  << FormShift,
    341 
    342     // Multiply instructions
    343     MulFrm        = 1  << FormShift,
    344 
    345     // Branch instructions
    346     BrFrm         = 2  << FormShift,
    347     BrMiscFrm     = 3  << FormShift,
    348 
    349     // Data Processing instructions
    350     DPFrm         = 4  << FormShift,
    351     DPSoRegFrm    = 5  << FormShift,
    352 
    353     // Load and Store
    354     LdFrm         = 6  << FormShift,
    355     StFrm         = 7  << FormShift,
    356     LdMiscFrm     = 8  << FormShift,
    357     StMiscFrm     = 9  << FormShift,
    358     LdStMulFrm    = 10 << FormShift,
    359 
    360     LdStExFrm     = 11 << FormShift,
    361 
    362     // Miscellaneous arithmetic instructions
    363     ArithMiscFrm  = 12 << FormShift,
    364     SatFrm        = 13 << FormShift,
    365 
    366     // Extend instructions
    367     ExtFrm        = 14 << FormShift,
    368 
    369     // VFP formats
    370     VFPUnaryFrm   = 15 << FormShift,
    371     VFPBinaryFrm  = 16 << FormShift,
    372     VFPConv1Frm   = 17 << FormShift,
    373     VFPConv2Frm   = 18 << FormShift,
    374     VFPConv3Frm   = 19 << FormShift,
    375     VFPConv4Frm   = 20 << FormShift,
    376     VFPConv5Frm   = 21 << FormShift,
    377     VFPLdStFrm    = 22 << FormShift,
    378     VFPLdStMulFrm = 23 << FormShift,
    379     VFPMiscFrm    = 24 << FormShift,
    380 
    381     // Thumb format
    382     ThumbFrm      = 25 << FormShift,
    383 
    384     // Miscelleaneous format
    385     MiscFrm       = 26 << FormShift,
    386 
    387     // NEON formats
    388     NGetLnFrm     = 27 << FormShift,
    389     NSetLnFrm     = 28 << FormShift,
    390     NDupFrm       = 29 << FormShift,
    391     NLdStFrm      = 30 << FormShift,
    392     N1RegModImmFrm= 31 << FormShift,
    393     N2RegFrm      = 32 << FormShift,
    394     NVCVTFrm      = 33 << FormShift,
    395     NVDupLnFrm    = 34 << FormShift,
    396     N2RegVShLFrm  = 35 << FormShift,
    397     N2RegVShRFrm  = 36 << FormShift,
    398     N3RegFrm      = 37 << FormShift,
    399     N3RegVShFrm   = 38 << FormShift,
    400     NVExtFrm      = 39 << FormShift,
    401     NVMulSLFrm    = 40 << FormShift,
    402     NVTBLFrm      = 41 << FormShift,
    403 
    404     //===------------------------------------------------------------------===//
    405     // Misc flags.
    406 
    407     // UnaryDP - Indicates this is a unary data processing instruction, i.e.
    408     // it doesn't have a Rn operand.
    409     UnaryDP       = 1 << 13,
    410 
    411     // Xform16Bit - Indicates this Thumb2 instruction may be transformed into
    412     // a 16-bit Thumb instruction if certain conditions are met.
    413     Xform16Bit    = 1 << 14,
    414 
    415     // ThumbArithFlagSetting - The instruction is a 16-bit flag setting Thumb
    416     // instruction. Used by the parser to determine whether to require the 'S'
    417     // suffix on the mnemonic (when not in an IT block) or preclude it (when
    418     // in an IT block).
    419     ThumbArithFlagSetting = 1 << 18,
    420 
    421     //===------------------------------------------------------------------===//
    422     // Code domain.
    423     DomainShift   = 15,
    424     DomainMask    = 7 << DomainShift,
    425     DomainGeneral = 0 << DomainShift,
    426     DomainVFP     = 1 << DomainShift,
    427     DomainNEON    = 2 << DomainShift,
    428     DomainNEONA8  = 4 << DomainShift,
    429 
    430     //===------------------------------------------------------------------===//
    431     // Field shifts - such shifts are used to set field while generating
    432     // machine instructions.
    433     //
    434     // FIXME: This list will need adjusting/fixing as the MC code emitter
    435     // takes shape and the ARMCodeEmitter.cpp bits go away.
    436     ShiftTypeShift = 4,
    437 
    438     M_BitShift     = 5,
    439     ShiftImmShift  = 5,
    440     ShiftShift     = 7,
    441     N_BitShift     = 7,
    442     ImmHiShift     = 8,
    443     SoRotImmShift  = 8,
    444     RegRsShift     = 8,
    445     ExtRotImmShift = 10,
    446     RegRdLoShift   = 12,
    447     RegRdShift     = 12,
    448     RegRdHiShift   = 16,
    449     RegRnShift     = 16,
    450     S_BitShift     = 20,
    451     W_BitShift     = 21,
    452     AM3_I_BitShift = 22,
    453     D_BitShift     = 22,
    454     U_BitShift     = 23,
    455     P_BitShift     = 24,
    456     I_BitShift     = 25,
    457     CondShift      = 28
    458   };
    459 
    460 } // end namespace ARMII
    461 
    462 } // end namespace llvm;
    463 
    464 #endif
    465