| /external/llvm/lib/Target/AArch64/ |
| AArch64StorePairSuppress.cpp | 148 unsigned BaseReg;
150 if (TII->getLdStBaseRegImmOfs(&MI, BaseReg, Offset, TRI)) {
151 if (PrevBaseReg == BaseReg) {
160 PrevBaseReg = BaseReg;
|
| AArch64LoadStoreOptimizer.cpp | 396 unsigned BaseReg = FirstMI->getOperand(1).getReg();
404 if (FirstMI->modifiesRegister(BaseReg, TRI))
439 if (BaseReg == MIBaseReg && ((Offset == MIOffset + OffsetStride) ||
513 if (ModifiedRegs[BaseReg])
606 static bool isMatchingUpdateInsn(MachineInstr *MI, unsigned BaseReg,
625 if (MI->getOperand(0).getReg() == BaseReg &&
626 MI->getOperand(1).getReg() == BaseReg &&
647 unsigned BaseReg = MemMI->getOperand(1).getReg();
653 if (DestReg == BaseReg || TRI->isSubRegister(BaseReg, DestReg)
[all...] |
| /external/llvm/lib/Target/ARM/InstPrinter/ |
| ARMInstPrinter.cpp | 247 unsigned BaseReg = MI->getOperand(0).getReg();
249 if (MI->getOperand(i).getReg() == BaseReg)
257 printRegName(O, BaseReg);
[all...] |
| /external/llvm/lib/Target/X86/InstPrinter/ |
| X86ATTInstPrinter.cpp | 186 const MCOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg);
201 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg()))
208 if (IndexReg.getReg() || BaseReg.getReg()) {
210 if (BaseReg.getReg())
|
| X86IntelInstPrinter.cpp | 166 const MCOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg);
181 if (BaseReg.getReg()) {
200 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) {
|
| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| MipsNaClELFStreamer.cpp | 122 unsigned BaseReg = MI.getOperand(AddrIdx).getReg();
123 emitMask(BaseReg, LoadStoreStackMaskReg, STI);
|
| /external/clang/lib/StaticAnalyzer/Core/ |
| Store.cpp | 285 const MemRegion *BaseReg =
289 return loc::MemRegionVal(BaseReg);
|
| /external/llvm/lib/CodeGen/ |
| LocalStackSlotAllocation.cpp | 327 unsigned BaseReg = 0;
365 DEBUG(dbgs() << " Reusing base register " << BaseReg << "\n");
392 BaseReg = Fn.getRegInfo().createVirtualRegister(RC);
394 DEBUG(dbgs() << " Materializing base register " << BaseReg <<
400 TRI->materializeFrameBaseRegister(Entry, BaseReg, FrameIdx,
411 assert(BaseReg != 0 && "Unable to allocate virtual base register!");
415 TRI->resolveFrameIndex(*I, BaseReg, Offset);
|
| CodeGenPrepare.cpp | [all...] |
| MachineScheduler.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86AsmPrinter.cpp | 235 const MachineOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg);
240 bool HasBaseReg = BaseReg.getReg() != 0;
242 BaseReg.getReg() == X86::RIP)
300 const MachineOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg);
315 if (BaseReg.getReg()) {
333 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) {
|
| X86MCInstLower.cpp | 691 unsigned Opc, BaseReg, ScaleVal, IndexReg, Displacement, SegmentReg;
693 BaseReg = X86::RAX; ScaleVal = 1;
728 OS.EmitInstruction(MCInstBuilder(Opc).addReg(BaseReg).addImm(ScaleVal)
[all...] |
| X86InstrInfo.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| Thumb2SizeReduction.cpp | 127 // ARM::t2STM (with no basereg writeback) has no Thumb1 equivalent
418 unsigned BaseReg = MI->getOperand(0).getReg();
419 if (!isARMLowRegister(BaseReg) || Entry.WideOpc != ARM::t2LDMIA)
426 if (MI->getOperand(i).getReg() == BaseReg) {
440 unsigned BaseReg = MI->getOperand(1).getReg();
441 if (BaseReg != ARM::SP)
454 unsigned BaseReg = MI->getOperand(1).getReg();
455 if (BaseReg == ARM::SP &&
460 } else if (!isARMLowRegister(BaseReg) ||
[all...] |
| ARMConstantIslandPass.cpp | [all...] |
| ARMLoadStoreOptimizer.cpp | [all...] |
| ARMBaseInstrInfo.cpp | 163 unsigned BaseReg = Base.getReg();
179 .addReg(BaseReg).addImm(Amt)
186 .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
191 .addReg(BaseReg).addReg(OffReg)
202 .addReg(BaseReg).addImm(Amt)
207 .addReg(BaseReg).addReg(OffReg)
229 .addReg(BaseReg).addImm(0).addImm(Pred);
233 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
[all...] |
| /external/llvm/lib/Target/Sparc/AsmParser/ |
| SparcAsmParser.cpp | 550 unsigned BaseReg = 0;
552 if (ParseRegister(BaseReg, S, E)) {
562 Operands.push_back(SparcOperand::CreateMEMri(BaseReg, nullptr, S, E));
578 Offset->isImm() ? SparcOperand::MorphToMEMri(BaseReg, std::move(Offset))
579 : SparcOperand::MorphToMEMrr(BaseReg, std::move(Offset)));
|
| /external/llvm/lib/Target/X86/AsmParser/ |
| X86Operand.h | 52 unsigned BaseReg;
113 return Mem.BaseReg;
449 Res->Mem.BaseReg = 0;
461 CreateMem(unsigned SegReg, const MCExpr *Disp, unsigned BaseReg,
467 assert((SegReg || BaseReg || IndexReg) && "Invalid memory operand!");
475 Res->Mem.BaseReg = BaseReg;
|
| X86AsmParser.cpp | 253 unsigned BaseReg, IndexReg, TmpReg, Scale;
262 State(IES_PLUS), PrevState(IES_ERROR), BaseReg(0), IndexReg(0), TmpReg(0),
266 unsigned getBaseReg() { return BaseReg; }
355 // If we already have a BaseReg, then assume this is the IndexReg with
357 if (!BaseReg) {
358 BaseReg = TmpReg;
360 assert (!IndexReg && "BaseReg/IndexReg already set!");
392 // If we already have a BaseReg, then assume this is the IndexReg with
394 if (!BaseReg) {
395 BaseReg = TmpReg
941 unsigned basereg = local
949 unsigned basereg = local
[all...] |
| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| X86MCCodeEmitter.cpp | 60 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
64 if (is16BitMode(STI) && BaseReg.getReg() == 0 &&
67 if ((BaseReg.getReg() != 0 &&
68 X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg.getReg())) ||
249 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
252 if ((BaseReg.getReg() != 0 &&
253 X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg.getReg())) ||
264 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
267 if ((BaseReg.getReg() != 0 &&
268 X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg.getReg())) |
[all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| LoopStrengthReduce.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | [all...] |
