1 //===-- AsmPrinterDwarf.cpp - AsmPrinter Dwarf Support --------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the Dwarf emissions parts of AsmPrinter. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "ByteStreamer.h" 15 #include "llvm/CodeGen/AsmPrinter.h" 16 #include "llvm/ADT/SmallBitVector.h" 17 #include "llvm/ADT/Twine.h" 18 #include "llvm/IR/DataLayout.h" 19 #include "llvm/MC/MCAsmInfo.h" 20 #include "llvm/MC/MCSection.h" 21 #include "llvm/MC/MCStreamer.h" 22 #include "llvm/MC/MCSymbol.h" 23 #include "llvm/MC/MachineLocation.h" 24 #include "llvm/Support/Dwarf.h" 25 #include "llvm/Support/ErrorHandling.h" 26 #include "llvm/Target/TargetFrameLowering.h" 27 #include "llvm/Target/TargetLoweringObjectFile.h" 28 #include "llvm/Target/TargetMachine.h" 29 #include "llvm/Target/TargetRegisterInfo.h" 30 using namespace llvm; 31 32 #define DEBUG_TYPE "asm-printer" 33 34 //===----------------------------------------------------------------------===// 35 // Dwarf Emission Helper Routines 36 //===----------------------------------------------------------------------===// 37 38 /// EmitSLEB128 - emit the specified signed leb128 value. 39 void AsmPrinter::EmitSLEB128(int64_t Value, const char *Desc) const { 40 if (isVerbose() && Desc) 41 OutStreamer.AddComment(Desc); 42 43 OutStreamer.EmitSLEB128IntValue(Value); 44 } 45 46 /// EmitULEB128 - emit the specified signed leb128 value. 47 void AsmPrinter::EmitULEB128(uint64_t Value, const char *Desc, 48 unsigned PadTo) const { 49 if (isVerbose() && Desc) 50 OutStreamer.AddComment(Desc); 51 52 OutStreamer.EmitULEB128IntValue(Value, PadTo); 53 } 54 55 /// EmitCFAByte - Emit a .byte 42 directive for a DW_CFA_xxx value. 56 void AsmPrinter::EmitCFAByte(unsigned Val) const { 57 if (isVerbose()) { 58 if (Val >= dwarf::DW_CFA_offset && Val < dwarf::DW_CFA_offset + 64) 59 OutStreamer.AddComment("DW_CFA_offset + Reg (" + 60 Twine(Val - dwarf::DW_CFA_offset) + ")"); 61 else 62 OutStreamer.AddComment(dwarf::CallFrameString(Val)); 63 } 64 OutStreamer.EmitIntValue(Val, 1); 65 } 66 67 static const char *DecodeDWARFEncoding(unsigned Encoding) { 68 switch (Encoding) { 69 case dwarf::DW_EH_PE_absptr: 70 return "absptr"; 71 case dwarf::DW_EH_PE_omit: 72 return "omit"; 73 case dwarf::DW_EH_PE_pcrel: 74 return "pcrel"; 75 case dwarf::DW_EH_PE_udata4: 76 return "udata4"; 77 case dwarf::DW_EH_PE_udata8: 78 return "udata8"; 79 case dwarf::DW_EH_PE_sdata4: 80 return "sdata4"; 81 case dwarf::DW_EH_PE_sdata8: 82 return "sdata8"; 83 case dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_udata4: 84 return "pcrel udata4"; 85 case dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_sdata4: 86 return "pcrel sdata4"; 87 case dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_udata8: 88 return "pcrel udata8"; 89 case dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_sdata8: 90 return "pcrel sdata8"; 91 case dwarf::DW_EH_PE_indirect | dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_udata4 92 : 93 return "indirect pcrel udata4"; 94 case dwarf::DW_EH_PE_indirect | dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_sdata4 95 : 96 return "indirect pcrel sdata4"; 97 case dwarf::DW_EH_PE_indirect | dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_udata8 98 : 99 return "indirect pcrel udata8"; 100 case dwarf::DW_EH_PE_indirect | dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_sdata8 101 : 102 return "indirect pcrel sdata8"; 103 } 104 105 return "<unknown encoding>"; 106 } 107 108 /// EmitEncodingByte - Emit a .byte 42 directive that corresponds to an 109 /// encoding. If verbose assembly output is enabled, we output comments 110 /// describing the encoding. Desc is an optional string saying what the 111 /// encoding is specifying (e.g. "LSDA"). 112 void AsmPrinter::EmitEncodingByte(unsigned Val, const char *Desc) const { 113 if (isVerbose()) { 114 if (Desc) 115 OutStreamer.AddComment(Twine(Desc) + " Encoding = " + 116 Twine(DecodeDWARFEncoding(Val))); 117 else 118 OutStreamer.AddComment(Twine("Encoding = ") + DecodeDWARFEncoding(Val)); 119 } 120 121 OutStreamer.EmitIntValue(Val, 1); 122 } 123 124 /// GetSizeOfEncodedValue - Return the size of the encoding in bytes. 125 unsigned AsmPrinter::GetSizeOfEncodedValue(unsigned Encoding) const { 126 if (Encoding == dwarf::DW_EH_PE_omit) 127 return 0; 128 129 switch (Encoding & 0x07) { 130 default: 131 llvm_unreachable("Invalid encoded value."); 132 case dwarf::DW_EH_PE_absptr: 133 return TM.getDataLayout()->getPointerSize(); 134 case dwarf::DW_EH_PE_udata2: 135 return 2; 136 case dwarf::DW_EH_PE_udata4: 137 return 4; 138 case dwarf::DW_EH_PE_udata8: 139 return 8; 140 } 141 } 142 143 void AsmPrinter::EmitTTypeReference(const GlobalValue *GV, 144 unsigned Encoding) const { 145 if (GV) { 146 const TargetLoweringObjectFile &TLOF = getObjFileLowering(); 147 148 const MCExpr *Exp = 149 TLOF.getTTypeGlobalReference(GV, Encoding, *Mang, TM, MMI, OutStreamer); 150 OutStreamer.EmitValue(Exp, GetSizeOfEncodedValue(Encoding)); 151 } else 152 OutStreamer.EmitIntValue(0, GetSizeOfEncodedValue(Encoding)); 153 } 154 155 /// EmitSectionOffset - Emit the 4-byte offset of Label from the start of its 156 /// section. This can be done with a special directive if the target supports 157 /// it (e.g. cygwin) or by emitting it as an offset from a label at the start 158 /// of the section. 159 /// 160 /// SectionLabel is a temporary label emitted at the start of the section that 161 /// Label lives in. 162 void AsmPrinter::EmitSectionOffset(const MCSymbol *Label, 163 const MCSymbol *SectionLabel) const { 164 // On COFF targets, we have to emit the special .secrel32 directive. 165 if (MAI->needsDwarfSectionOffsetDirective()) { 166 OutStreamer.EmitCOFFSecRel32(Label); 167 return; 168 } 169 170 // Get the section that we're referring to, based on SectionLabel. 171 const MCSection &Section = SectionLabel->getSection(); 172 173 // If Label has already been emitted, verify that it is in the same section as 174 // section label for sanity. 175 assert((!Label->isInSection() || &Label->getSection() == &Section) && 176 "Section offset using wrong section base for label"); 177 178 // If the section in question will end up with an address of 0 anyway, we can 179 // just emit an absolute reference to save a relocation. 180 if (Section.isBaseAddressKnownZero()) { 181 OutStreamer.EmitSymbolValue(Label, 4); 182 return; 183 } 184 185 // Otherwise, emit it as a label difference from the start of the section. 186 EmitLabelDifference(Label, SectionLabel, 4); 187 } 188 189 /// Emit a dwarf register operation. 190 static void emitDwarfRegOp(ByteStreamer &Streamer, int Reg) { 191 assert(Reg >= 0); 192 if (Reg < 32) { 193 Streamer.EmitInt8(dwarf::DW_OP_reg0 + Reg, 194 dwarf::OperationEncodingString(dwarf::DW_OP_reg0 + Reg)); 195 } else { 196 Streamer.EmitInt8(dwarf::DW_OP_regx, "DW_OP_regx"); 197 Streamer.EmitULEB128(Reg, Twine(Reg)); 198 } 199 } 200 201 /// Emit an (double-)indirect dwarf register operation. 202 static void emitDwarfRegOpIndirect(ByteStreamer &Streamer, int Reg, int Offset, 203 bool Deref) { 204 assert(Reg >= 0); 205 if (Reg < 32) { 206 Streamer.EmitInt8(dwarf::DW_OP_breg0 + Reg, 207 dwarf::OperationEncodingString(dwarf::DW_OP_breg0 + Reg)); 208 } else { 209 Streamer.EmitInt8(dwarf::DW_OP_bregx, "DW_OP_bregx"); 210 Streamer.EmitULEB128(Reg, Twine(Reg)); 211 } 212 Streamer.EmitSLEB128(Offset); 213 if (Deref) 214 Streamer.EmitInt8(dwarf::DW_OP_deref, "DW_OP_deref"); 215 } 216 217 /// Emit a dwarf register operation for describing 218 /// - a small value occupying only part of a register or 219 /// - a small register representing only part of a value. 220 static void emitDwarfOpPiece(ByteStreamer &Streamer, unsigned SizeInBits, 221 unsigned OffsetInBits) { 222 assert(SizeInBits > 0 && "zero-sized piece"); 223 unsigned SizeOfByte = 8; 224 if (OffsetInBits > 0 || SizeInBits % SizeOfByte) { 225 Streamer.EmitInt8(dwarf::DW_OP_bit_piece, "DW_OP_bit_piece"); 226 Streamer.EmitULEB128(SizeInBits, Twine(SizeInBits)); 227 Streamer.EmitULEB128(OffsetInBits, Twine(OffsetInBits)); 228 } else { 229 Streamer.EmitInt8(dwarf::DW_OP_piece, "DW_OP_piece"); 230 unsigned ByteSize = SizeInBits / SizeOfByte; 231 Streamer.EmitULEB128(ByteSize, Twine(ByteSize)); 232 } 233 } 234 235 /// Emit a shift-right dwarf expression. 236 static void emitDwarfOpShr(ByteStreamer &Streamer, 237 unsigned ShiftBy) { 238 Streamer.EmitInt8(dwarf::DW_OP_constu, "DW_OP_constu"); 239 Streamer.EmitULEB128(ShiftBy); 240 Streamer.EmitInt8(dwarf::DW_OP_shr, "DW_OP_shr"); 241 } 242 243 // Some targets do not provide a DWARF register number for every 244 // register. This function attempts to emit a DWARF register by 245 // emitting a piece of a super-register or by piecing together 246 // multiple subregisters that alias the register. 247 void AsmPrinter::EmitDwarfRegOpPiece(ByteStreamer &Streamer, 248 const MachineLocation &MLoc, 249 unsigned PieceSizeInBits, 250 unsigned PieceOffsetInBits) const { 251 assert(MLoc.isReg() && "MLoc must be a register"); 252 const TargetRegisterInfo *TRI = TM.getRegisterInfo(); 253 int Reg = TRI->getDwarfRegNum(MLoc.getReg(), false); 254 255 // If this is a valid register number, emit it. 256 if (Reg >= 0) { 257 emitDwarfRegOp(Streamer, Reg); 258 emitDwarfOpPiece(Streamer, PieceSizeInBits, PieceOffsetInBits); 259 return; 260 } 261 262 // Walk up the super-register chain until we find a valid number. 263 // For example, EAX on x86_64 is a 32-bit piece of RAX with offset 0. 264 for (MCSuperRegIterator SR(MLoc.getReg(), TRI); SR.isValid(); ++SR) { 265 Reg = TRI->getDwarfRegNum(*SR, false); 266 if (Reg >= 0) { 267 unsigned Idx = TRI->getSubRegIndex(*SR, MLoc.getReg()); 268 unsigned Size = TRI->getSubRegIdxSize(Idx); 269 unsigned Offset = TRI->getSubRegIdxOffset(Idx); 270 OutStreamer.AddComment("super-register"); 271 emitDwarfRegOp(Streamer, Reg); 272 if (PieceOffsetInBits == Offset) { 273 emitDwarfOpPiece(Streamer, Size, Offset); 274 } else { 275 // If this is part of a variable in a sub-register at a 276 // non-zero offset, we need to manually shift the value into 277 // place, since the DW_OP_piece describes the part of the 278 // variable, not the position of the subregister. 279 emitDwarfOpPiece(Streamer, Size, PieceOffsetInBits); 280 if (Offset) 281 emitDwarfOpShr(Streamer, Offset); 282 } 283 return; 284 } 285 } 286 287 // Otherwise, attempt to find a covering set of sub-register numbers. 288 // For example, Q0 on ARM is a composition of D0+D1. 289 // 290 // Keep track of the current position so we can emit the more 291 // efficient DW_OP_piece. 292 unsigned CurPos = PieceOffsetInBits; 293 // The size of the register in bits, assuming 8 bits per byte. 294 unsigned RegSize = TRI->getMinimalPhysRegClass(MLoc.getReg())->getSize() * 8; 295 // Keep track of the bits in the register we already emitted, so we 296 // can avoid emitting redundant aliasing subregs. 297 SmallBitVector Coverage(RegSize, false); 298 for (MCSubRegIterator SR(MLoc.getReg(), TRI); SR.isValid(); ++SR) { 299 unsigned Idx = TRI->getSubRegIndex(MLoc.getReg(), *SR); 300 unsigned Size = TRI->getSubRegIdxSize(Idx); 301 unsigned Offset = TRI->getSubRegIdxOffset(Idx); 302 Reg = TRI->getDwarfRegNum(*SR, false); 303 304 // Intersection between the bits we already emitted and the bits 305 // covered by this subregister. 306 SmallBitVector Intersection(RegSize, false); 307 Intersection.set(Offset, Offset + Size); 308 Intersection ^= Coverage; 309 310 // If this sub-register has a DWARF number and we haven't covered 311 // its range, emit a DWARF piece for it. 312 if (Reg >= 0 && Intersection.any()) { 313 OutStreamer.AddComment("sub-register"); 314 emitDwarfRegOp(Streamer, Reg); 315 emitDwarfOpPiece(Streamer, Size, Offset == CurPos ? 0 : Offset); 316 CurPos = Offset + Size; 317 318 // Mark it as emitted. 319 Coverage.set(Offset, Offset + Size); 320 } 321 } 322 323 if (CurPos == PieceOffsetInBits) { 324 // FIXME: We have no reasonable way of handling errors in here. 325 Streamer.EmitInt8(dwarf::DW_OP_nop, 326 "nop (could not find a dwarf register number)"); 327 } 328 } 329 330 /// EmitDwarfRegOp - Emit dwarf register operation. 331 void AsmPrinter::EmitDwarfRegOp(ByteStreamer &Streamer, 332 const MachineLocation &MLoc, 333 bool Indirect) const { 334 const TargetRegisterInfo *TRI = TM.getRegisterInfo(); 335 int Reg = TRI->getDwarfRegNum(MLoc.getReg(), false); 336 if (Reg < 0) { 337 // We assume that pointers are always in an addressable register. 338 if (Indirect || MLoc.isIndirect()) { 339 // FIXME: We have no reasonable way of handling errors in here. The 340 // caller might be in the middle of a dwarf expression. We should 341 // probably assert that Reg >= 0 once debug info generation is more 342 // mature. 343 Streamer.EmitInt8(dwarf::DW_OP_nop, 344 "nop (invalid dwarf register number for indirect loc)"); 345 return; 346 } 347 348 // Attempt to find a valid super- or sub-register. 349 return EmitDwarfRegOpPiece(Streamer, MLoc); 350 } 351 352 if (MLoc.isIndirect()) 353 emitDwarfRegOpIndirect(Streamer, Reg, MLoc.getOffset(), Indirect); 354 else if (Indirect) 355 emitDwarfRegOpIndirect(Streamer, Reg, 0, false); 356 else 357 emitDwarfRegOp(Streamer, Reg); 358 } 359 360 //===----------------------------------------------------------------------===// 361 // Dwarf Lowering Routines 362 //===----------------------------------------------------------------------===// 363 364 void AsmPrinter::emitCFIInstruction(const MCCFIInstruction &Inst) const { 365 switch (Inst.getOperation()) { 366 default: 367 llvm_unreachable("Unexpected instruction"); 368 case MCCFIInstruction::OpDefCfaOffset: 369 OutStreamer.EmitCFIDefCfaOffset(Inst.getOffset()); 370 break; 371 case MCCFIInstruction::OpDefCfa: 372 OutStreamer.EmitCFIDefCfa(Inst.getRegister(), Inst.getOffset()); 373 break; 374 case MCCFIInstruction::OpDefCfaRegister: 375 OutStreamer.EmitCFIDefCfaRegister(Inst.getRegister()); 376 break; 377 case MCCFIInstruction::OpOffset: 378 OutStreamer.EmitCFIOffset(Inst.getRegister(), Inst.getOffset()); 379 break; 380 case MCCFIInstruction::OpRegister: 381 OutStreamer.EmitCFIRegister(Inst.getRegister(), Inst.getRegister2()); 382 break; 383 case MCCFIInstruction::OpWindowSave: 384 OutStreamer.EmitCFIWindowSave(); 385 break; 386 case MCCFIInstruction::OpSameValue: 387 OutStreamer.EmitCFISameValue(Inst.getRegister()); 388 break; 389 } 390 } 391
