| /external/chromium_org/sandbox/linux/seccomp-bpf/ |
| instruction.h | 15 // code -- Opcode of the instruction. This is typically a bitwise
26 struct Instruction {
27 // Constructor for an non-jumping instruction or for an unconditional
29 Instruction(uint16_t c, uint32_t parm, Instruction* n)
32 // Constructor for a conditional jump instruction.
33 Instruction(uint16_t c, uint32_t parm, Instruction* jt, Instruction* jf)
49 Instruction* jt_ptr, *jf_ptr
[all...] |
| /external/llvm/lib/IR/ |
| Instruction.cpp | 1 //===-- Instruction.cpp - Implement the Instruction class -----------------===//
10 // This file implements the Instruction class for the IR library.
14 #include "llvm/IR/Instruction.h"
24 Instruction::Instruction(Type *ty, unsigned it, Use *Ops, unsigned NumOps,
25 Instruction *InsertBefore)
30 // If requested, insert this instruction into a basic block...
33 "Instruction to insert before is not in a basic block!");
38 const DataLayout *Instruction::getDataLayout() const
[all...] |
| /external/chromium_org/chrome/tools/profile_reset/ |
| jtl_compiler.cc | 46 // each instruction from a parsed text-based format to byte-code.
50 // Define each instruction in this list.
56 Add(Instruction("go", jtl::NAVIGATE, Arguments(String)));
57 Add(Instruction("any", jtl::NAVIGATE_ANY, Arguments()));
58 Add(Instruction("back", jtl::NAVIGATE_BACK, Arguments()));
59 Add(Instruction("store_bool", jtl::STORE_BOOL, Arguments(String, Bool)));
60 Add(Instruction("store_hash",
62 Add(Instruction("store_hashed",
64 Add(Instruction("store_node_bool",
66 Add(Instruction("store_node_hash"
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/nv50/codegen/ |
| nv50_ir.cpp | 101 Instruction *insn = src->value->getUniqueInsn();
173 if (!insn || !insn->bb) // Unbound instruction ?
180 Instruction *insn = (*it)->getInsn();
276 Instruction *insn = getInsn();
552 void Instruction::init()
582 Instruction::Instruction()
593 Instruction::Instruction(Function *fn, operation opr, DataType ty)
603 Instruction::~Instruction(
[all...] |
| nv50_ir_from_tgsi.cpp | 41 class Instruction
44 Instruction(const struct tgsi_full_instruction *inst) : insn(inst) { }
156 inline uint getOpcode() const { return insn->Instruction.Opcode; }
158 unsigned int srcCount() const { return insn->Instruction.NumSrcRegs; }
159 unsigned int dstCount() const { return insn->Instruction.NumDstRegs; }
198 unsigned getSaturate() const { return insn->Instruction.Saturate; }
209 unsigned int Instruction::srcMask(unsigned int s) const
213 switch (insn->Instruction.Opcode) {
248 assert(insn->Instruction.Texture);
251 if (insn->Instruction.Opcode != TGSI_OPCODE_TEX &
[all...] |
| /external/lldb/source/Core/ |
| Disassembler.cpp | 424 Instruction *inst = disasm_ptr->GetInstructionList().GetInstructionAtIndex (i).get();
555 Instruction::Instruction(const Address &address, AddressClass addr_class) :
563 Instruction::~Instruction()
568 Instruction::GetAddressClass ()
576 Instruction::Dump (lldb_private::Stream *s,
647 Instruction::DumpEmulation (const ArchSpec &arch)
660 Instruction::ReadArray (FILE *in_file, Stream *out_stream, OptionValue::Type data_type)
672 out_stream->Printf ("Instruction::ReadArray: Error reading file (fgets).\n")
[all...] |
| /external/mesa3d/src/gallium/drivers/nv50/codegen/ |
| nv50_ir.cpp | 101 Instruction *insn = src->value->getUniqueInsn();
173 if (!insn || !insn->bb) // Unbound instruction ?
180 Instruction *insn = (*it)->getInsn();
276 Instruction *insn = getInsn();
552 void Instruction::init()
582 Instruction::Instruction()
593 Instruction::Instruction(Function *fn, operation opr, DataType ty)
603 Instruction::~Instruction(
[all...] |
| nv50_ir_from_tgsi.cpp | 41 class Instruction
44 Instruction(const struct tgsi_full_instruction *inst) : insn(inst) { }
156 inline uint getOpcode() const { return insn->Instruction.Opcode; }
158 unsigned int srcCount() const { return insn->Instruction.NumSrcRegs; }
159 unsigned int dstCount() const { return insn->Instruction.NumDstRegs; }
198 unsigned getSaturate() const { return insn->Instruction.Saturate; }
209 unsigned int Instruction::srcMask(unsigned int s) const
213 switch (insn->Instruction.Opcode) {
248 assert(insn->Instruction.Texture);
251 if (insn->Instruction.Opcode != TGSI_OPCODE_TEX &
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/auxiliary/tgsi/ |
| tgsi_parse.h | 95 struct tgsi_instruction Instruction;
|
| /external/chromium_org/third_party/skia/third_party/lua/src/ |
| llimits.h | 133 typedef lu_int32 Instruction;
|
| /external/lldb/include/lldb/Core/ |
| Disassembler.h | 30 class Instruction
33 Instruction (const Address &address,
37 ~Instruction();
129 Address m_address; // The section offset address of this instruction
130 // We include an address class in the Instruction class to
131 // allow the instruction specify the eAddressClassCodeAlternateISA
139 Opcode m_opcode; // The opcode for this instruction
199 public Instruction
214 // TODO: fill this in and put opcode name into Instruction::m_opcode_name,
215 // mnemonic into Instruction::m_mnemonics, and any comment into
[all...] |
| /external/llvm/bindings/python/llvm/ |
| core.py | 30 "Instruction",
343 return i and Instruction(i)
348 return i and Instruction(i)
384 if not isinstance(self.inst, Instruction):
400 class Instruction(Value):
408 return i and Instruction(i)
413 return i and Instruction(i)
582 # Instruction Declarations.
583 library.LLVMGetNextInstruction.argtypes = [Instruction]
586 library.LLVMGetPreviousInstruction.argtypes = [Instruction]
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| /external/llvm/lib/DebugInfo/ |
| DWARFDebugFrame.cpp | 60 /// An entry may contain CFI instructions. An instruction consists of an
63 struct Instruction {
64 Instruction(uint8_t Opcode)
72 std::vector<Instruction> Instructions;
74 /// Convenience methods to add a new instruction with the given opcode and
77 Instructions.push_back(Instruction(Opcode));
81 Instructions.push_back(Instruction(Opcode));
86 Instructions.push_back(Instruction(Opcode));
184 // TODO: at the moment only instruction names are dumped. Expand this to
|
| /external/mesa3d/src/gallium/auxiliary/tgsi/ |
| tgsi_parse.h | 95 struct tgsi_instruction Instruction;
|
| /external/chromium_org/courgette/ |
| assembly_program.cc | 39 class Instruction {
44 explicit Instruction(OP op) : op_(op), info_(0) {}
45 Instruction(OP op, unsigned int info) : op_(op), info_(info) {}
51 DISALLOW_COPY_AND_ASSIGN(Instruction);
57 class OriginInstruction : public Instruction {
59 explicit OriginInstruction(RVA rva) : Instruction(ORIGIN, 0), rva_(rva) {}
66 class PeRelocsInstruction : public Instruction {
68 PeRelocsInstruction() : Instruction(MAKEPERELOCS) {}
72 class ElfRelocsInstruction : public Instruction {
74 ElfRelocsInstruction() : Instruction(MAKEELFRELOCS) {
149 Instruction* instruction = instructions_[i]; local
406 Instruction* instruction = instructions_[i]; local
523 Instruction* instruction = instructions_[i]; local
[all...] |
| /external/llvm/include/llvm/IR/ |
| Instruction.h | 1 //===-- llvm/Instruction.h - Instruction class definition -------*- C++ -*-===//
10 // This file contains the declaration of the Instruction class, which is the
32 class Instruction : public User, public ilist_node<Instruction> {
33 void operator=(const Instruction &) LLVM_DELETED_FUNCTION;
34 Instruction(const Instruction &) LLVM_DELETED_FUNCTION;
41 /// indicates whether this instruction has metadata attached to it or not.
46 ~Instruction();
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/i915/ |
| i915_fpc.h | 297 struct tgsi_instruction Instruction;
|
| /external/chromium_org/v8/src/arm64/ |
| instructions-arm64.h | 86 // instruction (such as with fcvta). It cannot be set in FPCR.
97 class Instruction {
124 V8_INLINE Instruction* following(int count = 1) {
128 V8_INLINE Instruction* preceding(int count = 1) {
219 // does not check that the instruction actually has an Rd field.
248 // does not check that the instruction actually has an Rn field.
291 // The range of the branch instruction, expressed as 'instr +- range'.
329 // A marking nop is an instruction
338 // Find the PC offset encoded in this instruction. 'this' may be a branch or
339 // a PC-relative addressing instruction
[all...] |
| /external/mesa3d/src/gallium/drivers/i915/ |
| i915_fpc.h | 297 struct tgsi_instruction Instruction;
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/r300/compiler/ |
| radeon_pair_schedule.c | 45 struct rc_instruction * Instruction;
47 /** Next instruction in the linked list of ready instructions. */
50 /** Values that this instruction reads and writes */
58 * this instruction can be scheduled.
63 * "all readers"), even those outside the basic block this instruction
67 /** If the scheduler has paired an RGB and an Alpha instruction together,
73 * instruction to schedule. Instructions with a higher value of Score
77 /** The number of components that read from a TEX instruction. */
111 * of the instruction writing \ref Next is decremented.
190 fprintf(stderr,"%u (%d) [%u],", ptr->Instruction->IP, score
[all...] |
| /external/llvm/lib/MC/ |
| MCStreamer.cpp | 288 MCCFIInstruction Instruction =
291 CurFrame->Instructions.push_back(Instruction);
296 MCCFIInstruction Instruction =
299 CurFrame->Instructions.push_back(Instruction);
304 MCCFIInstruction Instruction =
307 CurFrame->Instructions.push_back(Instruction);
312 MCCFIInstruction Instruction =
315 CurFrame->Instructions.push_back(Instruction);
320 MCCFIInstruction Instruction =
323 CurFrame->Instructions.push_back(Instruction);
[all...] |
| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| radeon_pair_schedule.c | 45 struct rc_instruction * Instruction;
47 /** Next instruction in the linked list of ready instructions. */
50 /** Values that this instruction reads and writes */
58 * this instruction can be scheduled.
63 * "all readers"), even those outside the basic block this instruction
67 /** If the scheduler has paired an RGB and an Alpha instruction together,
73 * instruction to schedule. Instructions with a higher value of Score
77 /** The number of components that read from a TEX instruction. */
111 * of the instruction writing \ref Next is decremented.
190 fprintf(stderr,"%u (%d) [%u],", ptr->Instruction->IP, score
[all...] |
| /art/runtime/ |
| dex_instruction.h | 35 class Instruction {
176 // Returns the size (in 2 byte code units) of this instruction.
186 // Reads an instruction out of the stream at the specified address.
187 static const Instruction* At(const uint16_t* code) {
189 return reinterpret_cast<const Instruction*>(code);
192 // Reads an instruction out of the stream from the current address plus an offset.
193 const Instruction* RelativeAt(int32_t offset) const {
197 // Returns a pointer to the next instruction in the stream.
198 const Instruction* Next() const {
202 // Returns a pointer to the instruction after this 1xx instruction in the stream
[all...] |
| /external/chromium_org/v8/src/compiler/ |
| instruction.h | 15 #include "src/compiler/instruction-codes.h"
109 // Lifetime of operand inside the instruction.
112 // instruction start. Register allocator is free to assign the same register
113 // to some other operand used inside instruction (i.e. temporary or
118 // instruction. This means that register allocator will not reuse it's
119 // register for any other operand inside instruction.
404 class Instruction : public ZoneObject {
438 static Instruction* New(Zone* zone, InstructionCode opcode) {
442 static Instruction* New(Zone* zone, InstructionCode opcode,
452 int size = static_cast<int>(RoundUp(sizeof(Instruction), kPointerSize)
[all...] |
| /external/chromium_org/v8/src/arm/ |
| constants-arm.h | 17 // Use UDF, the permanently undefined instruction.
122 // Instruction objects are pointers to 32bit values, and provide methods to
162 // Instruction encoding bits and masks.
169 A = 1 << 21, // Accumulate in multiply instruction (or not).
196 // Instruction bit masks.
199 kRdMask = 15 << 12, // In str instruction.
211 // Addressing modes and instruction variants.
409 // Instruction abstraction.
411 // The class Instruction enables access to individual fields defined in the ARM
412 // architecture instruction set encoding as described in figure A3-1
[all...] |
