| /external/chromium_org/sandbox/linux/seccomp-bpf/ |
| codegen.h | 18 typedef std::vector<Instruction*> Instructions;
25 // graph of BPF instructions into a well-formed stream of BPF instructions.
27 // the limit of 255 instructions imposed by the instruction set.
30 // build a DAG of Instructions. They'll eventually call Compile() to convert
63 // Create a new instruction. Instructions form a DAG. The instruction objects
75 // Traverse the graph of instructions and visit each instruction once.
83 // Compiles the graph of instructions into a BPF program that can be passed
86 void Compile(Instruction* instructions, SandboxBPF::Program* program);
91 // Find all the instructions that are the target of BPF_JMPs
[all...] |
| /external/llvm/include/llvm/MC/ |
| MCWin64EH.h | 68 ChainedParent(nullptr), Instructions() {}
79 std::vector<MCWin64EHInstruction> Instructions;
|
| MCDwarf.h | 155 /// for a compile unit where machine instructions have been assembled after seeing
403 /// was at the beginning of the function, after all initial instructions added
469 Instructions(), PersonalityEncoding(), LsdaEncoding(0),
475 std::vector<MCCFIInstruction> Instructions;
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64AddressTypePromotion.cpp | 38 #include "llvm/IR/Instructions.h"
82 // sext instructions.
101 typedef SmallVector<Instruction *, 16> Instructions;
102 typedef DenseMap<Value *, Instructions> ValueToInsts;
119 /// Move sext operations through safe to sext instructions.
120 bool propagateSignExtension(Instructions &SExtInsts);
134 void analyzeSExtension(Instructions &SExtInsts);
226 // - SExtInsts contains all the sext instructions that are use direclty in
251 AArch64AddressTypePromotion::propagateSignExtension(Instructions &SExtInsts) {
344 // If more sext are required, new instructions will have to be created
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/r300/compiler/ |
| radeon_dataflow_deadcode.c | 61 struct instruction_state * Instructions;
155 struct instruction_state * insts = &s->Instructions[inst->IP];
225 s.Instructions = memory_pool_malloc(&c->Pool, sizeof(struct instruction_state)*nr_instructions);
226 memset(s.Instructions, 0, sizeof(struct instruction_state)*nr_instructions);
230 for(struct rc_instruction * inst = c->Program.Instructions.Prev;
231 inst != &c->Program.Instructions;
313 for(struct rc_instruction * inst = c->Program.Instructions.Next;
314 inst != &c->Program.Instructions;
324 inst->U.I.DstReg.WriteMask = s.Instructions[ip].WriteMask;
325 if (s.Instructions[ip].WriteMask
[all...] |
| radeon_program.h | 70 * Instructions are maintained by the compiler in a doubly linked list
101 * \name Extra fields for TEX, TXB, TXD, TXL, TXP instructions.
153 * Instructions.Next points to the first instruction,
154 * Instructions.Prev points to the last instruction.
156 struct rc_instruction Instructions;
|
| /external/llvm/lib/DebugInfo/ |
| DWARFDebugFrame.cpp | 38 /// \brief Parse and store a sequence of CFI instructions from Data,
48 /// \brief Dump the entry's instructions to the given output stream.
60 /// An entry may contain CFI instructions. An instruction consists of an
72 std::vector<Instruction> Instructions;
75 /// operands to the Instructions vector.
77 Instructions.push_back(Instruction(Opcode));
81 Instructions.push_back(Instruction(Opcode));
82 Instructions.back().Ops.push_back(Operand1);
86 Instructions.push_back(Instruction(Opcode));
87 Instructions.back().Ops.push_back(Operand1)
[all...] |
| /external/llvm/tools/bugpoint/ |
| CrashDebugger.cpp | 21 #include "llvm/IR/Instructions.h"
355 /// non-terminator instructions and replacing them with undef.
386 SmallPtrSet<Instruction*, 64> Instructions;
389 Instructions.insert(cast<Instruction>(VMap[Insts[i]]));
392 outs() << "Checking for crash with only " << Instructions.size();
393 if (Instructions.size() == 1)
396 outs() << " instructions: ";
402 if (!Instructions.count(Inst) && !isa<TerminatorInst>(Inst) &&
423 for (SmallPtrSet<Instruction*, 64>::const_iterator I = Instructions.begin(),
424 E = Instructions.end(); I != E; ++I
[all...] |
| /external/llvm/utils/TableGen/ |
| CodeGenTarget.h | 68 mutable DenseMap<const Record*, CodeGenInstruction*> Instructions;
150 if (Instructions.empty()) ReadInstructions();
151 return Instructions;
156 if (Instructions.empty()) ReadInstructions();
158 Instructions.find(InstRec);
159 assert(I != Instructions.end() && "Not an instruction");
163 /// getInstructionsByEnumValue - Return all of the instructions defined by the
174 iterator_range<inst_iterator> instructions() const { function in class:llvm::CodeGenTarget
184 /// encodings, reverse the bit order of all instructions.
|
| AsmWriterEmitter.cpp | 41 std::vector<AsmWriterInst> Instructions;
87 /// instructions that are suitably similar to it.
101 // If this differs in the same operand as the rest of the instructions in
117 // If the operand is the same for all instructions, just print it.
120 // If this is the operand that varies between all of the instructions,
151 // instructions each case are used for. It is a comma separated string of
189 // For each entry of UniqueOperandCommands, there is a set of instructions
190 // that uses it. If the next command of all instructions in the set are
208 // Otherwise, scan to see if all of the other instructions in this command
244 // Prepend some of the instructions each case is used for onto the case val
[all...] |
| CodeGenDAGPatterns.cpp | 11 // represent the patterns present in a .td file for instructions.
[all...] |
| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| radeon_dataflow_deadcode.c | 61 struct instruction_state * Instructions;
155 struct instruction_state * insts = &s->Instructions[inst->IP];
225 s.Instructions = memory_pool_malloc(&c->Pool, sizeof(struct instruction_state)*nr_instructions);
226 memset(s.Instructions, 0, sizeof(struct instruction_state)*nr_instructions);
230 for(struct rc_instruction * inst = c->Program.Instructions.Prev;
231 inst != &c->Program.Instructions;
313 for(struct rc_instruction * inst = c->Program.Instructions.Next;
314 inst != &c->Program.Instructions;
324 inst->U.I.DstReg.WriteMask = s.Instructions[ip].WriteMask;
325 if (s.Instructions[ip].WriteMask
[all...] |
| radeon_program.h | 70 * Instructions are maintained by the compiler in a doubly linked list
101 * \name Extra fields for TEX, TXB, TXD, TXL, TXP instructions.
153 * Instructions.Next points to the first instruction,
154 * Instructions.Prev points to the last instruction.
156 struct rc_instruction Instructions;
|
| /external/chromium_org/third_party/mesa/src/src/mesa/program/ |
| nvfragparse.c | 87 static const struct instruction_pattern Instructions[] = {
152 GLuint numInst; /* number of instructions parsed */
226 for (inst = Instructions; inst->name; inst++) {
[all...] |
| /external/chromium_org/third_party/sfntly/cpp/src/sfntly/table/truetype/ |
| glyph_table.cc | 350 CALLER_ATTACH ReadableFontData* GlyphTable::SimpleGlyph::Instructions() {
611 CALLER_ATTACH ReadableFontData* GlyphTable::CompositeGlyph::Instructions() {
|
| /external/chromium_org/third_party/skia/src/sfnt/ |
| SkOTTable_glyf.h | 77 struct Instructions {
205 struct Instructions {
|
| /external/llvm/lib/Target/Sparc/AsmParser/ |
| SparcAsmParser.cpp | 1 //===-- SparcAsmParser.cpp - Parse Sparc assembly to MCInst instructions --===//
392 SmallVector<MCInst, 8> Instructions;
|
| /external/llvm/lib/Transforms/Scalar/ |
| LoopRerollPass.cpp | 65 // of isomorphic DAGs of instructions, with each DAG rooted at some increment
84 // where each f(i) is a set of instructions that, collectively, are a function
152 // A chain of isomorphic instructions, indentified by a single-use PHI,
157 : Valid(false), Instructions(1, P) {
168 return Instructions.front();
173 return Instructions.back();
178 return Instructions[i+1];
186 return Instructions.size()-1;
194 return std::next(Instructions.begin());
199 return std::next(Instructions.begin())
[all...] |
| /external/mesa3d/src/mesa/program/ |
| nvfragparse.c | 87 static const struct instruction_pattern Instructions[] = {
152 GLuint numInst; /* number of instructions parsed */
226 for (inst = Instructions; inst->name; inst++) {
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/auxiliary/tgsi/ |
| tgsi_exec.h | 271 const struct tgsi_token *Tokens; /**< Declarations, instructions */
328 struct tgsi_full_instruction *Instructions;
|
| /external/llvm/include/llvm/CodeGen/ |
| MachineBasicBlock.h | 10 // Collect the sequence of machine instructions for a basic block.
63 typedef ilist<MachineInstr> Instructions;
64 Instructions Insts;
205 typedef Instructions::iterator instr_iterator;
206 typedef Instructions::const_iterator const_instr_iterator;
372 /// updateTerminator - Update the terminator instructions in block to account
440 /// PHINode instruction. When adding instructions to the beginning of the
482 /// alone can't be used to prepend or append instructions to bundles. See
486 /// Insert a range of instructions into the instruction list before I.
508 /// If the instruction is part of a bundle, the other instructions in th
[all...] |
| /external/llvm/lib/MC/ |
| MCDwarf.cpp | [all...] |
| /external/mesa3d/src/gallium/auxiliary/tgsi/ |
| tgsi_exec.h | 271 const struct tgsi_token *Tokens; /**< Declarations, instructions */
328 struct tgsi_full_instruction *Instructions;
|
| /external/llvm/lib/Target/Mips/AsmParser/ |
| MipsAsmParser.cpp | 1 //===-- MipsAsmParser.cpp - Parse Mips assembly to MCInst instructions ----===//
119 // Expands assembly pseudo instructions.
122 SmallVectorImpl<MCInst> &Instructions);
125 SmallVectorImpl<MCInst> &Instructions);
128 SmallVectorImpl<MCInst> &Instructions);
131 SmallVectorImpl<MCInst> &Instructions);
134 SmallVectorImpl<MCInst> &Instructions, bool isLoad,
196 SmallVectorImpl<MCInst> &Instructions);
901 SmallVectorImpl<MCInst> &Instructions) {
[all...] |
| /external/chromium_org/third_party/mesa/src/src/mesa/main/ |
| mtypes.h | [all...] |
