| /external/llvm/lib/Target/NVPTX/ |
| NVPTXFrameLowering.cpp | 39 MachineBasicBlock::iterator MBBI = MBB.begin();
51 BuildMI(MBB, MBBI, dl,
60 BuildMI(MBB, MBBI, dl,
|
| /external/llvm/lib/CodeGen/ |
| SlotIndexes.cpp | 177 MachineBasicBlock::iterator MBBI = End;
179 while (ListI != ListB || MBBI != Begin || (includeStart && !pastStart)) {
185 MachineInstr *MI = (MBBI != MBB->end() && !pastStart) ? MBBI : nullptr;
186 bool MBBIAtBegin = MBBI == Begin && (!includeStart || pastStart);
190 if (MBBI != Begin)
191 --MBBI;
195 if (MBBI != Begin)
196 --MBBI;
|
| MachineFunction.cpp | 140 MachineFunction::iterator MBBI, E = end();
142 MBBI = begin();
144 MBBI = MBB;
148 if (MBBI != begin())
149 BlockNo = std::prev(MBBI)->getNumber() + 1;
151 for (; MBBI != E; ++MBBI, ++BlockNo) {
152 if (MBBI->getNumber() != (int)BlockNo) {
154 if (MBBI->getNumber() != -1) {
155 assert(MBBNumbering[MBBI->getNumber()] == &*MBBI &
[all...] |
| SplitKit.cpp | 646 MachineBasicBlock::iterator MBBI(MI);
648 do AtBegin = MBBI == MBB->begin();
649 while (!AtBegin && (--MBBI)->isDebugValue());
666 if (AtBegin || !MBBI->readsVirtualRegister(Edit->getReg())) {
670 SlotIndex Kill = LIS.getInstructionIndex(MBBI).getRegSlot();
671 DEBUG(dbgs() << " move kill to " << Kill << '\t' << *MBBI);
[all...] |
| BranchFolding.cpp | 425 MachineFunction::iterator MBBI = &CurMBB;
427 CurMBB.getParent()->insert(++MBBI, NewMBB);
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64A53Fix835769.cpp | 129 MachineFunction::iterator MBBI = *MBB;
132 if (MBBI == MBB->getParent()->begin())
138 MachineBasicBlock *PrevBB = std::prev(MBBI);
|
| AArch64BranchRelaxation.cpp | 133 MachineFunction::iterator MBBI = MBB;
135 MachineBasicBlock *NextBB = std::next(MBBI);
218 MachineFunction::iterator MBBI = OrigBB;
219 ++MBBI;
220 MF->insert(MBBI, NewBB);
|
| AArch64LoadStoreOptimizer.cpp | 388 MachineBasicBlock::iterator MBBI = I;
390 ++MBBI;
416 for (unsigned Count = 0; MBBI != E && Count < Limit; ++MBBI) {
417 MachineInstr *MI = MBBI;
475 return MBBI;
484 return MBBI;
643 MachineBasicBlock::iterator MBBI = I;
667 ++MBBI;
668 for (unsigned Count = 0; MBBI != E; ++MBBI)
[all...] |
| AArch64FrameLowering.cpp | 155 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
162 DebugLoc DL = MBB.findDebugLoc(MBBI);
197 BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
204 MachineBasicBlock::iterator MBBI = MBB.begin();
214 DebugLoc DL = MBB.findDebugLoc(MBBI);
229 emitFrameOffset(MBB, MBBI, DL, AArch64::SP, AArch64::SP, -NumBytes, TII,
235 BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
249 assert((MBBI->getOpcode() == AArch64::STPXpre ||
250 MBBI->getOpcode() == AArch64::STPDpre) &&
251 MBBI->getOperand(3).getReg() == AArch64::SP &
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMInstrInfo.cpp | 121 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
122 DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
128 MachineInstrBuilder MIB = BuildMI(FirstMBB, MBBI, DL,
139 MIB = BuildMI(FirstMBB, MBBI, DL, TII.get(Opc), GlobalBaseReg)
|
| Thumb2InstrInfo.cpp | 63 MachineBasicBlock::iterator MBBI = Tail;
66 --MBBI;
75 while (Count && MBBI != E) {
76 if (MBBI->isDebugValue()) {
77 --MBBI;
80 if (MBBI->getOpcode() == ARM::t2IT) {
81 unsigned Mask = MBBI->getOperand(1).getImm();
83 MBBI->eraseFromParent();
87 MBBI->getOperand(1).setImm((Mask & MaskOff) | MaskOn);
91 --MBBI;
[all...] |
| Thumb1FrameLowering.cpp | 42 MachineBasicBlock::iterator &MBBI,
46 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, TII,
87 MachineBasicBlock::iterator MBBI = MBB.begin();
103 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
118 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -ArgRegsSaveSize,
123 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
129 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -(NumBytes - ArgRegsSaveSize),
134 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
167 if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH)
[all...] |
| Thumb2ITBlockPass.cpp | 167 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
168 while (MBBI != E) {
169 MachineInstr *MI = &*MBBI;
174 ++MBBI;
183 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(ARM::t2IT))
192 ++MBBI;
203 for (; MBBI != E && Pos &&
204 (!MI->isBranch() && !MI->isReturn()) ; ++MBBI) {
205 if (MBBI->isDebugValue())
208 MachineInstr *NMI = &*MBBI;
[all...] |
| ARMExpandPseudoInsts.cpp | 61 MachineBasicBlock::iterator MBBI);
63 void ExpandVLD(MachineBasicBlock::iterator &MBBI);
64 void ExpandVST(MachineBasicBlock::iterator &MBBI);
65 void ExpandLaneOp(MachineBasicBlock::iterator &MBBI);
66 void ExpandVTBL(MachineBasicBlock::iterator &MBBI,
69 MachineBasicBlock::iterator &MBBI);
380 void ARMExpandPseudo::ExpandVLD(MachineBasicBlock::iterator &MBBI) {
381 MachineInstr &MI = *MBBI;
389 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
445 void ARMExpandPseudo::ExpandVST(MachineBasicBlock::iterator &MBBI) {
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| RegisterScavenging.h | 36 MachineBasicBlock::iterator MBBI;
66 /// before MBBI. One bit per physical register. If bit is set that means it's
93 while (MBBI != I) forward();
102 while (MBBI != I) unprocess();
109 MBBI = I;
113 return MBBI;
157 return scavengeRegister(RegClass, MBBI, SPAdj);
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430FrameLowering.cpp | 48 MachineBasicBlock::iterator MBBI = MBB.begin();
49 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
66 BuildMI(MBB, MBBI, DL, TII.get(MSP430::PUSH16r))
70 BuildMI(MBB, MBBI, DL, TII.get(MSP430::MOV16rr), MSP430::FPW)
82 while (MBBI != MBB.end() && (MBBI->getOpcode() == MSP430::PUSH16r))
83 ++MBBI;
85 if (MBBI != MBB.end())
86 DL = MBBI->getDebugLoc()
[all...] |
| /external/llvm/lib/Target/Mips/ |
| Mips16FrameLowering.cpp | 40 MachineBasicBlock::iterator MBBI = MBB.begin();
41 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
52 TII.makeFrame(Mips::SP, StackSize, MBB, MBBI);
57 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
72 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
77 BuildMI(MBB, MBBI, dl, TII.get(Mips::MoveR3216), Mips::S0)
84 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
88 DebugLoc dl = MBBI->getDebugLoc();
95 BuildMI(MBB, MBBI, dl, TII.get(Mips::Move32R16), Mips::SP
[all...] |
| MipsOptimizePICCall.cpp | 75 bool visitNode(MBBInfo &MBBI);
187 MBBInfo &MBBI = WorkList.back();
191 if (MBBI.isVisited()) {
192 MBBI.postVisit();
198 MBBI.preVisit(ScopedHT);
199 Changed |= visitNode(MBBI);
200 const MachineDomTreeNode *Node = MBBI.getNode();
208 bool OptimizePICCall::visitNode(MBBInfo &MBBI) {
210 MachineBasicBlock *MBB = MBBI.getNode()->getBlock();
|
| MipsSEFrameLowering.cpp | 285 MachineBasicBlock::iterator MBBI = MBB.begin();
286 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
303 TII.adjustStackPtr(SP, -StackSize, MBB, MBBI);
308 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
317 ++MBBI;
339 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
344 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
350 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
364 TII.storeRegToStackSlot(MBB, MBBI, ehDataReg(I), false
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcFrameLowering.cpp | 42 MachineBasicBlock::iterator MBBI,
47 DebugLoc dl = (MBBI != MBB.end()) ? MBBI->getDebugLoc() : DebugLoc();
52 BuildMI(MBB, MBBI, dl, TII.get(ADDri), SP::O6)
64 BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1)
66 BuildMI(MBB, MBBI, dl, TII.get(SP::ORri), SP::G1)
68 BuildMI(MBB, MBBI, dl, TII.get(ADDrr), SP::O6)
77 BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1)
79 BuildMI(MBB, MBBI, dl, TII.get(SP::XORri), SP::G1)
81 BuildMI(MBB, MBBI, dl, TII.get(ADDrr), SP::O6
[all...] |
| SparcInstrInfo.cpp | 434 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
443 BuildMI(FirstMBB, MBBI, dl, get(SP::GETPCX), GlobalBaseReg);
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonFrameLowering.cpp | 79 MachineBasicBlock::iterator MBBI = MBB.begin();
82 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
139 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
140 unsigned RetOpcode = MBBI->getOpcode();
147 MachineBasicBlock::iterator MBBI = std::prev(MBB.end());
148 DebugLoc dl = MBBI->getDebugLoc();
154 MachineBasicBlock::iterator MBBI = std::prev(MBB.end());
159 if (MBBI->getOpcode() == Hexagon::EH_RETURN_JMPR) {
160 assert(MBBI->getOperand(0).isReg() && "Offset should be in register!")
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZElimCompare.cpp | 192 MachineBasicBlock::iterator MBBI = Compare, MBBE = Branch;
193 for (++MBBI; MBBI != MBBE; ++MBBI)
194 if (getRegReferences(MBBI, SrcReg))
295 MachineBasicBlock::iterator MBBI = MI, MBBE = Compare;
296 for (++MBBI; MBBI != MBBE; ++MBBI)
297 MBBI->clearRegisterKills(SystemZ::CC, TRI)
[all...] |
| SystemZFrameLowering.cpp | 123 MachineBasicBlock::iterator MBBI,
133 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
174 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(SystemZ::STMG));
202 TII->storeRegToStackSlot(MBB, MBBI, Reg, true, CSI[I].getFrameIdx(),
212 MachineBasicBlock::iterator MBBI,
222 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
228 TII->loadRegFromStackSlot(MBB, MBBI, Reg, CSI[I].getFrameIdx(),
244 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(SystemZ::LMG))
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreFrameLowering.cpp | 62 MachineBasicBlock::iterator MBBI, DebugLoc dl,
67 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
72 MachineBasicBlock::iterator MBBI, DebugLoc dl,
77 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
82 MachineBasicBlock::iterator MBBI, DebugLoc dl,
87 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
98 MachineBasicBlock::iterator MBBI, DebugLoc dl,
107 BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(OpImm);
110 EmitDefCfaOffset(MBB, MBBI, dl, TII, MMI, Adjusted*4);
122 MachineBasicBlock::iterator MBBI, DebugLoc dl
[all...] |
