| /external/chromium_org/third_party/leveldatabase/src/util/ |
| crc32c.h | 31 inline uint32_t Mask(uint32_t crc) {
|
| /art/runtime/base/ |
| bit_field.h | 37 // Returns a uword mask of the bit field.
38 static uword Mask() {
42 // Returns a uword mask of the bit field which can be applied directly to
|
| /external/llvm/lib/CodeGen/ |
| StackMapLivenessAnalysis.cpp | 113 uint32_t *Mask = createRegisterMask();
114 MachineOperand MO = MachineOperand::CreateRegLiveOut(Mask);
118 /// Create a register mask and initialize it with the registers from the
121 // The mask is owned and cleaned up by the Machine Function.
122 uint32_t *Mask = MF->allocateRegisterMask(TRI->getNumRegs());
125 Mask[*RI / 32] |= 1U << (*RI % 32);
126 return Mask;
|
| /external/llvm/tools/llvm-readobj/ |
| ARMWinEHPrinter.h | 29 uint8_t Mask;
|
| ARMEHABIPrinter.h | 33 uint8_t Mask;
63 void PrintRegisters(uint32_t Mask, StringRef Prefix);
295 if ((Opcodes[OCI ^ 3] & Ring[REI].Mask) == Ring[REI].Value) {
|
| /external/clang/include/clang/AST/ |
| DeclAccessPair.h | 33 enum { Mask = 0x3 };
43 return reinterpret_cast<NamedDecl*>(~Mask & Ptr);
46 return AccessSpecifier(Mask & Ptr);
|
| /external/llvm/lib/Target/ARM/ |
| Thumb2InstrInfo.cpp | 81 unsigned Mask = MBBI->getOperand(1).getImm();
87 MBBI->getOperand(1).setImm((Mask & MaskOff) | MaskOn);
587 unsigned Mask = (1 << NumBits) - 1;
588 if ((unsigned)Offset <= Mask * Scale) {
604 ImmedOffset = ImmedOffset & Mask;
617 Offset &= ~(Mask*Scale);
|
| Thumb1RegisterInfo.cpp | 382 unsigned Mask = (1 << NumBits) - 1;
383 if (((Offset / Scale) & ~Mask) == 0) {
416 AddDefaultPred(AddDefaultT1CC(MIB).addReg(FrameReg).addImm(Mask));
419 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Mask);
421 Offset = (Offset - Mask * Scale);
451 unsigned Mask = (1 << NumBits) - 1;
453 if ((unsigned)Offset <= Mask * Scale) {
468 Mask = (1 << NumBits) - 1;
476 ImmedOffset = ImmedOffset & Mask;
478 Offset &= ~(Mask * Scale)
[all...] |
| Thumb2ITBlockPass.cpp | 196 unsigned Mask = 0, Pos = 3;
214 Mask |= (NCC & 1) << Pos;
235 // Finalize IT mask.
236 Mask |= (1 << Pos);
237 // Tag along (firstcond[0] << 4) with the mask.
238 Mask |= (CC & 1) << 4;
239 MIB.addImm(Mask);
|
| ARMBaseRegisterInfo.cpp | 107 // This should return a register mask that is the same as that returned by
694 unsigned Mask = (1 << NumBits) - 1;
695 if ((unsigned)Offset <= Mask * Scale)
|
| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| MipsAsmBackend.cpp | 209 uint64_t Mask = ((uint64_t)(-1) >>
211 CurVal |= Value & Mask;
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZRegisterInfo.cpp | 92 int64_t Mask = 0xffff;
94 Offset = OldOffset & Mask;
96 Mask >>= 1;
97 assert(Mask && "One offset must be OK");
|
| /external/llvm/lib/Target/X86/ |
| X86FloatingPoint.cpp | 90 // Bit mask of live FP registers. Bit 0 = FP0, bit 1 = FP1, &c.
91 unsigned Mask;
101 LiveBundle() : Mask(0), FixCount(0) {}
104 bool isFixed() const { return !Mask || FixCount; }
116 unsigned Mask = 0;
122 Mask |= 1 << (Reg - X86::FP0);
124 return Mask;
297 /// Adjust the live registers to be the set in Mask.
298 void adjustLiveRegs(unsigned Mask, MachineBasicBlock::iterator I);
398 const unsigned Mask = calcLiveInMask(MBB)
[all...] |
| /external/llvm/lib/Target/R600/ |
| R600ExpandSpecialInstrs.cpp | 205 bool Mask = (Chan != TRI.getHWRegChan(DstReg));
213 if (Mask) {
297 bool Mask = false;
303 // Mask the write if the original instruction does not write to
305 Mask = (Chan != TRI.getHWRegChan(DstReg));
331 if (Mask) {
|
| R600TextureIntrinsicsReplacer.cpp | 125 Constant *Mask[] = {
131 Value *SwizzleMask = ConstantVector::get(Mask);
|
| /external/llvm/include/llvm/ADT/ |
| BitVector.h | 180 // Mask off previous bits.
256 BitWord Mask = EMask - IMask;
257 Bits[I / BITWORD_SIZE] |= Mask;
295 BitWord Mask = EMask - IMask;
296 Bits[I / BITWORD_SIZE] &= ~Mask;
334 BitWord Mask = BitWord(1) << (Idx % BITWORD_SIZE);
335 return (Bits[Idx / BITWORD_SIZE] & Mask) != 0;
483 // Portable bit mask operations.
491 // bit mask is always a whole multiple of 32 bits. If no bit mask size i
[all...] |
| SmallBitVector.h | 231 // Mask off previous bits.
310 uintptr_t Mask = EMask - IMask;
311 setSmallBits(getSmallBits() | Mask);
341 uintptr_t Mask = EMask - IMask;
342 setSmallBits(getSmallBits() & ~Mask);
520 /// setBitsInMask - Add '1' bits from Mask to this vector. Don't resize.
521 /// This computes "*this |= Mask".
522 void setBitsInMask(const uint32_t *Mask, unsigned MaskWords = ~0u) {
524 applyMask<true, false>(Mask, MaskWords);
526 getPointer()->setBitsInMask(Mask, MaskWords)
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| MachineInstr.h | 166 unsigned Mask = BundledPred | BundledSucc;
167 Flags = (Flags & Mask) | (flags & ~Mask);
[all...] |
| /external/llvm/lib/Analysis/ |
| CostModel.cpp | 91 static bool isReverseVectorMask(SmallVectorImpl<int> &Mask) {
92 for (unsigned i = 0, MaskSize = Mask.size(); i < MaskSize; ++i)
93 if (Mask[i] > 0 && Mask[i] != (int)(MaskSize - 1 - i))
98 static bool isAlternateVectorMask(SmallVectorImpl<int> &Mask) {
100 unsigned MaskSize = Mask.size();
104 if (Mask[i] < 0)
106 isAlternate = Mask[i] == (int)((i & 1) ? MaskSize + i : i);
115 if (Mask[i] < 0)
117 isAlternate = Mask[i] == (int)((i & 1) ? i : MaskSize + i)
[all...] |
| /external/chromium_org/chromeos/network/onc/ |
| onc_utils.cc | 247 static scoped_ptr<base::DictionaryValue> Mask(
250 const std::string& mask) {
251 OncMaskValues masker(mask);
257 explicit OncMaskValues(const std::string& mask)
258 : mask_(mask) {
275 // Mask to insert in place of the sensitive values.
284 const std::string& mask) {
285 return OncMaskValues::Mask(signature, onc_object, mask);
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/r300/compiler/ |
| radeon_optimize.c | 40 unsigned int Mask;
113 && (rc_swizzle_to_writemask(src->Swizzle) & sc_data->Mask)) {
128 unsigned int mask)
134 sc_data.Mask = mask;
674 unsigned int mask)
677 if (rc_src_reads_dst_mask(file, mask, index,
689 unsigned int mask)
693 (mask & d->Writer->WriteMask)) {
|
| /external/llvm/include/llvm/Support/ |
| MathExtras.h | 60 T Mask = std::numeric_limits<T>::max() >> Shift;
62 if ((Val & Mask) == 0) {
67 Mask >>= Shift;
|
| /external/llvm/lib/ExecutionEngine/RuntimeDyld/ |
| RuntimeDyldChecker.cpp | 510 uint64_t Mask = ((uint64_t)1 << (HighBit - LowBit + 1)) - 1;
511 uint64_t SlicedValue = (SubExprResult.getValue() >> LowBit) & Mask;
|
| /external/llvm/lib/IR/ |
| Attributes.cpp | 503 uint64_t Mask = 0;
515 Mask |= (Log2_32(ASN->getAlignment()) + 1) << 16;
517 Mask |= (Log2_32(ASN->getStackAlignment()) + 1) << 26;
519 Mask |= AttributeImpl::getAttrMask(Kind);
522 return Mask;
[all...] |
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineShifts.cpp | 236 APInt Mask(APInt::getLowBitsSet(TypeWidth, TypeWidth - NumBits));
238 ConstantInt::get(BO->getContext(), Mask));
276 APInt Mask(APInt::getHighBitsSet(TypeWidth, TypeWidth - NumBits));
278 ConstantInt::get(BO->getContext(), Mask));
385 // The mask we constructed says what the trunc would do if occurring
388 // mask as appropriate.
430 Constant *Mask = ConstantInt::get(I.getContext(), Bits);
432 Mask = ConstantVector::getSplat(VT->getNumElements(), Mask);
433 return BinaryOperator::CreateAnd(X, Mask);
[all...] |
