/external/chromium_org/third_party/icu/source/test/intltest/ |
tscoll.h | 26 struct Order 28 int32_t order; member in struct:IntlTestCollator::Order 51 Order *getOrders(CollationElementIterator &iter, int32_t &orderLength);
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/external/icu/icu4c/source/test/intltest/ |
tscoll.h | 26 struct Order 28 int32_t order; member in struct:IntlTestCollator::Order 51 Order *getOrders(CollationElementIterator &iter, int32_t &orderLength);
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/external/aac/libAACdec/src/ |
aacdec_tns.h | 99 TNS_MAXIMUM_ORDER = 20, /* 12 for AAC-LC and AAC-SSR. Set to 20 for AAC-Main (AOT 1). Some broken encoders also do order 20 for AAC-LC :( */ 113 UCHAR Order;
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/external/chromium_org/skia/ext/ |
recursive_gaussian_convolution.h | 21 enum Order { 29 SK_API RecursiveFilter(float sigma, Order order); 31 Order order() const { return order_; } function in class:skia::RecursiveFilter 35 Order order_;
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/external/chromium_org/third_party/skia/experimental/PdfViewer/pdfparser/native/pdfapi/ |
SkPdfType0FunctionDictionary_autogen.cpp | 35 int64_t SkPdfType0FunctionDictionary::Order(SkPdfNativeDoc* doc) { 36 SkPdfNativeObject* ret = get("Order", ""); 44 return get("Order", "") != NULL;
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/external/llvm/lib/CodeGen/ |
AllocationOrder.h | 1 //===-- llvm/CodeGen/AllocationOrder.h - Allocation Order -*- C++ -*-------===// 10 // This file implements an allocation order for virtual registers. 12 // The preferred allocation order for a virtual register depends on allocation 30 ArrayRef<MCPhysReg> Order; 42 /// Get the allocation order without reordered hints. 43 ArrayRef<MCPhysReg> getOrder() const { return Order; } 45 /// Return the next physical register in the allocation order, or 0. 52 Limit = Order.size(); 54 unsigned Reg = Order[Pos++]; 62 /// Limit'th register in the RegisterClassInfo allocation order [all...] |
AtomicExpandLoadLinkedPass.cpp | 135 AtomicOrdering Order = AI->getOrdering(); 166 AtomicOrdering MemOpOrder = insertLeadingFence(Builder, Order); 225 insertTrailingFence(Builder, Order);
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TargetRegisterInfo.cpp | 133 ArrayRef<MCPhysReg> Order = RC->getRawAllocationOrder(MF); 134 for (unsigned i = 0; i != Order.size(); ++i) 135 R.set(Order[i]); 265 ArrayRef<MCPhysReg> Order, 287 // Check that Phys is in the allocation order. We shouldn't heed hints 288 // from VirtReg's register class if they aren't in the allocation order. The 290 if (std::find(Order.begin(), Order.end(), Phys) == Order.end())
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CriticalAntiDepBreaker.cpp | 406 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(RC); 407 for (unsigned i = 0; i != Order.size(); ++i) { 408 unsigned NewReg = Order[i]; 560 // the anti-dependencies in an instruction in order to be effective.
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/external/chromium_org/third_party/webrtc/base/ |
bytebuffer.h | 25 ORDER_NETWORK = 0, // Default, use network byte order (big endian). 26 ORDER_HOST, // Use the native order of the host. 29 // |byte_order| defines order of bytes in the buffer. 43 ByteOrder Order() const { return byte_order_; }
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/external/chromium_org/third_party/mesa/src/src/egl/main/ |
eglmode.c | 208 EGLint Order; /* SMALLER or LARGER */ 211 /* the order of these entries is the priority */ 242 else if (SortInfo[i].Order == SMALLER) { 245 else if (SortInfo[i].Order == LARGER) {
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/external/mesa3d/src/egl/main/ |
eglmode.c | 208 EGLint Order; /* SMALLER or LARGER */ 211 /* the order of these entries is the priority */ 242 else if (SortInfo[i].Order == SMALLER) { 245 else if (SortInfo[i].Order == LARGER) {
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/external/llvm/include/llvm/CodeGen/ |
RegisterClassInfo.h | 33 std::unique_ptr<MCPhysReg[]> Order; 40 return makeArrayRef(Order.get(), NumRegs); 90 /// getOrder - Returns the preferred allocation order for RC. The order 116 /// Get the minimum register cost in RC's allocation order.
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/external/llvm/lib/CodeGen/SelectionDAG/ |
SDNodeDbgValue.h | 51 unsigned Order; 58 Offset(off), DL(dl), Order(O), 68 mdPtr(mdP), IsIndirect(false), Offset(off), DL(dl), Order(O), 76 mdPtr(mdP), IsIndirect(false), Offset(off), DL(dl), Order(O), 109 // Returns the SDNodeOrder. This is the order of the preceding node in the 111 unsigned getOrder() { return Order; }
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SelectionDAGDumper.cpp | 509 if (unsigned Order = getIROrder()) 510 OS << " [ORD=" << Order << ']';
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/external/llvm/lib/Target/X86/ |
X86AtomicExpandPass.cpp | 210 AtomicOrdering Order = 256 Addr, Loaded, NewVal, Order, 257 AtomicCmpXchgInst::getStrongestFailureOrdering(Order)); 273 AtomicOrdering Order = 277 SI->getValueOperand(), Order);
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/external/lzma/CPP/7zip/UI/Common/ |
ZipRegistry.h | 31 UInt32 Order;
42 BlockLogSize = NumThreads = Level = Dictionary = Order = UInt32(-1);
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/external/lzma/CS/7zip/ |
ICoder.cs | 93 /// Specifies order for PPM methods.
95 Order,
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/external/chromium_org/third_party/leveldatabase/src/doc/bench/ |
db_bench_tree_db.cc | 12 // Comma-separated list of operations to run in the specified order 15 // fillseq -- write N values in sequential key order in async mode 16 // fillrandom -- write N values in random key order in async mode 17 // overwrite -- overwrite N values in random key order in async mode 18 // fillseqsync -- write N/100 values in sequential key order in sync mode 19 // fillrandsync -- write N/100 values in random key order in sync mode 20 // fillrand100K -- write N/1000 100K values in random order in async mode 21 // fillseq100K -- write N/1000 100K values in seq order in async mode 23 // readseq100K -- read N/1000 100K values in sequential order in async mode 24 // readrand100K -- read N/1000 100K values in sequential order in async mod [all...] |
db_bench_sqlite3.cc | 12 // Comma-separated list of operations to run in the specified order 15 // fillseq -- write N values in sequential key order in async mode 16 // fillseqsync -- write N/100 values in sequential key order in sync mode 17 // fillseqbatch -- batch write N values in sequential key order in async mode 18 // fillrandom -- write N values in random key order in async mode 19 // fillrandsync -- write N/100 values in random key order in sync mode 20 // fillrandbatch -- batch write N values in sequential key order in async mode 21 // overwrite -- overwrite N values in random key order in async mode 22 // fillrand100K -- write N/1000 100K values in random order in async mode 23 // fillseq100K -- write N/1000 100K values in sequential order in async mod [all...] |
/external/eigen/unsupported/Eigen/src/Splines/ |
Spline.h | 109 * \brief Evaluation of spline derivatives of up-to given order. 115 * for i ranging between 0 and order. 118 * \param order The order up to which the derivatives are computed. 121 derivatives(Scalar u, DenseIndex order) const; 130 derivatives(Scalar u, DenseIndex order = DerivativeOrder) const; 152 * \brief Computes the non-zero spline basis function derivatives up to given order. 158 * with i ranging from 0 up to the specified order. 162 * \param order The order up to which the basis function derivatives are computes [all...] |
/external/chromium_org/third_party/WebKit/Source/devtools/front_end/ui/ |
DataGrid.js | 160 /** @typedef {!{id: ?string, editable: boolean, longText: ?boolean, sort: !WebInspector.DataGrid.Order, sortable: boolean, align: !WebInspector.DataGrid.Align}} */ 171 WebInspector.DataGrid.Order = { 433 if (!this._sortColumnCell || this._sortColumnCell.classList.contains(WebInspector.DataGrid.Order.Ascending)) 434 return WebInspector.DataGrid.Order.Ascending; 435 if (this._sortColumnCell.classList.contains(WebInspector.DataGrid.Order.Descending)) 436 return WebInspector.DataGrid.Order.Descending; 445 return !this._sortColumnCell || this._sortColumnCell.classList.contains(WebInspector.DataGrid.Order.Ascending); 577 // width of the parent element is changed in order to make it possible to 708 // header table in order to determine the width of the column, since 860 var sortOrder = WebInspector.DataGrid.Order.Ascending [all...] |
/external/llvm/lib/MC/ |
MachObjectWriter.cpp | 466 // when we see the attribute, but that makes getting the order in the symbol 552 // The particular order that we collect the symbols and create the string 622 // External and undefined symbols are required to be in lexicographic order. 643 const SmallVectorImpl<MCSectionData*> &Order = Layout.getSectionOrder(); 644 for (int i = 0, n = Order.size(); i != n ; ++i) { 645 const MCSectionData *SD = Order[i]; [all...] |
/external/llvm/utils/TableGen/ |
RegisterInfoEmitter.cpp | 259 PSets.push_back(RegBank.getRegPressureSet(*PSetI).Order); 854 ArrayRef<Record*> Order = RC.getOrder(); 863 for (unsigned i = 0, e = Order.size(); i != e; ++i) { 864 Record *Reg = Order[i]; 873 for (unsigned i = 0, e = Order.size(); i != e; ++i) { 874 Record *Reg = Order[i]; [all...] |
/external/clang/lib/CodeGen/ |
CGAtomic.cpp | 309 llvm::AtomicOrdering Order) { 319 FailureOrder, Size, Align, Order); 323 FailureOrder, Size, Align, Order); 329 Val1, Val2, FailureOrder, Size, Align, Order); 343 FailureOrder, Size, Align, Order); 348 FailureOrder, Size, Align, Order); 359 Load->setAtomic(Order); 374 Store->setAtomic(Order); 437 CGF.Builder.CreateAtomicRMW(Op, Ptr, LoadVal1, Order); 502 llvm::Value *Order = EmitScalarExpr(E->getOrder()) [all...] |