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    Searched defs:RegIndex (Results 1 - 4 of 4) sorted by null

  /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
R600ISelLowering.cpp 99 int64_t RegIndex = MI->getOperand(1).getImm();
100 unsigned ConstantReg = AMDGPU::R600_CReg32RegClass.getRegister(RegIndex);
261 int64_t RegIndex = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
262 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex);
282 int64_t RegIndex = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
283 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex);
  /external/llvm/lib/Target/R600/
AMDGPUInstrInfo.cpp 136 unsigned RegIndex = MI->getOperand(RegOpIdx).getImm();
138 unsigned Address = calculateIndirectAddress(RegIndex, Channel);
151 unsigned RegIndex = MI->getOperand(RegOpIdx).getImm();
153 unsigned Address = calculateIndirectAddress(RegIndex, Channel);
160 calculateIndirectAddress(RegIndex, Channel),
299 unsigned RegIndex;
301 for (RegIndex = 0, RegEnd = IndirectRC->getNumRegs(); RegIndex != RegEnd;
302 ++RegIndex) {
303 if (IndirectRC->getRegister(RegIndex) == Reg
    [all...]
R600ISelLowering.cpp 597 int64_t RegIndex = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
598 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex);
630 int64_t RegIndex = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
631 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex);
    [all...]
  /external/mesa3d/src/gallium/drivers/radeon/
R600ISelLowering.cpp 99 int64_t RegIndex = MI->getOperand(1).getImm();
100 unsigned ConstantReg = AMDGPU::R600_CReg32RegClass.getRegister(RegIndex);
261 int64_t RegIndex = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
262 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex);
282 int64_t RegIndex = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
283 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex);

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