| /external/llvm/lib/Target/R600/ |
| SILowerI1Copies.cpp | 113 const TargetRegisterClass *SrcRC =
117 TRI->getCommonSubClass(SrcRC, &AMDGPU::SGPR_64RegClass)) {
130 SrcRC == &AMDGPU::VReg_1RegClass) {
|
| SIFixSGPRCopies.cpp | 185 const TargetRegisterClass *SrcRC;
192 SrcRC = TRI->getSubRegClass(MRI.getRegClass(SrcReg), SrcSubReg);
193 return TRI->isSGPRClass(DstRC) && TRI->hasVGPRs(SrcRC);
|
| SIInstrInfo.cpp | [all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXInstrInfo.cpp | 40 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg);
42 if (DestRC != SrcRC)
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| InstrEmitter.cpp | 156 const TargetRegisterClass *SrcRC = nullptr, *DstRC = nullptr;
157 SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT);
171 if (MatchReg && SrcRC->getCopyCost() < 0) {
[all...] |
| /external/llvm/lib/CodeGen/ |
| PeepholeOptimizer.cpp | 455 const TargetRegisterClass *SrcRC,
458 if (DefRC == SrcRC)
464 return TRI.getCommonSuperRegClass(SrcRC, SrcSubReg, DefRC, DefSubReg,
470 std::swap(DefRC, SrcRC);
475 return TRI.getMatchingSuperRegClass(SrcRC, DefRC, SrcSubReg) != nullptr;
477 return TRI.getCommonSubClass(DefRC, SrcRC) != nullptr;
569 const TargetRegisterClass *SrcRC = MRI->getRegClass(Src);
572 ShouldRewrite = shareSameRegisterFile(TRI, DefRC, DefSubReg, SrcRC,
[all...] |
| RegisterCoalescer.cpp | 290 const TargetRegisterClass *SrcRC = MRI.getRegClass(Src);
299 NewRC = TRI.getCommonSuperRegClass(SrcRC, SrcSub, DstRC, DstSub,
306 NewRC = TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSub);
310 NewRC = TRI.getMatchingSuperRegClass(SrcRC, DstRC, SrcSub);
313 NewRC = TRI.getCommonSubClass(DstRC, SrcRC);
328 CrossClass = NewRC != DstRC || NewRC != SrcRC;
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCInstrInfo.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMFastISel.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86FastISel.cpp | [all...] |
