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  /external/llvm/lib/CodeGen/
OptimizePHIs.cpp 103 unsigned SrcReg = MI->getOperand(i).getReg();
104 if (SrcReg == DstReg)
106 MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
124 SingleValReg = SrcReg;
RegisterCoalescer.h 35 /// SrcReg - the virtual register that will be coalesced into dstReg.
36 unsigned SrcReg;
42 /// SrcIdx - The sub-register index of the old SrcReg in the new coalesced
52 /// Flipped - True when DstReg and SrcReg are reversed from the original
58 /// SrcReg and DstReg.
63 : TRI(tri), DstReg(0), SrcReg(0), DstIdx(0), SrcIdx(0),
70 : TRI(tri), DstReg(PhysReg), SrcReg(VirtReg), DstIdx(0), SrcIdx(0),
77 /// flip - Swap SrcReg and DstReg. Return false if swapping is impossible
105 unsigned getSrcReg() const { return SrcReg; }
111 /// getSrcIdx - Return the subregister index that SrcReg will be coalesce
    [all...]
MachineSSAUpdater.cpp 96 unsigned SrcReg = I->getOperand(i).getReg();
98 if (AVals[SrcBB] != SrcReg) {
MachineSink.cpp 119 unsigned SrcReg = MI->getOperand(1).getReg();
121 if (!TargetRegisterInfo::isVirtualRegister(SrcReg) ||
123 !MRI->hasOneNonDBGUse(SrcReg))
126 const TargetRegisterClass *SRC = MRI->getRegClass(SrcReg);
131 MachineInstr *DefMI = MRI->getVRegDef(SrcReg);
136 MRI->replaceRegWith(DstReg, SrcReg);
MachineCSE.cpp 132 unsigned SrcReg = DefMI->getOperand(1).getReg();
133 if (!TargetRegisterInfo::isVirtualRegister(SrcReg))
141 // RC = TRI->getMatchingSuperRegClass(MRI->getRegClass(SrcReg), RC,
143 // MO.substVirtReg(SrcReg, SrcSubReg, *TRI);
152 if (!MRI->constrainRegClass(SrcReg, RC))
156 MO.setReg(SrcReg);
157 MRI->clearKillFlags(SrcReg);
PHIElimination.cpp 358 unsigned SrcReg = MPhi->getOperand(i*2+1).getReg();
361 isImplicitlyDefined(SrcReg, MRI);
362 assert(TargetRegisterInfo::isVirtualRegister(SrcReg) &&
378 findPHICopyInsertPoint(&opBlock, &MBB, SrcReg);
392 if (MachineInstr *DefMI = MRI->getVRegDef(SrcReg))
398 .addReg(SrcReg, 0, SrcSubReg);
402 // We only need to update the LiveVariables kill of SrcReg if this was the
403 // last PHI use of SrcReg to be lowered on this CFG edge and it is not live
406 !VRegPHIUseCount[BBVRegPair(opBlock.getNumber(), SrcReg)] &&
407 !LV->isLiveOut(SrcReg, opBlock))
    [all...]
  /external/llvm/lib/Target/Hexagon/
HexagonExpandPredSpillCode.cpp 87 // STriw_pred [R30], ofst, SrcReg;
93 int SrcReg = MI->getOperand(2).getReg();
94 assert(Hexagon::PredRegsRegClass.contains(SrcReg) &&
105 HEXAGON_RESERVED_REG_2).addReg(SrcReg);
114 HEXAGON_RESERVED_REG_2).addReg(SrcReg);
123 HEXAGON_RESERVED_REG_2).addReg(SrcReg);
HexagonPeephole.cpp 143 unsigned SrcReg = Src.getReg();
146 TargetRegisterInfo::isVirtualRegister(SrcReg)) {
150 PeepholeMap[DstReg] = SrcReg;
165 unsigned SrcReg = Src2.getReg();
166 PeepholeMap[DstReg] = SrcReg;
182 unsigned SrcReg = Src1.getReg();
184 std::make_pair(*&SrcReg, 1/*Hexagon::subreg_hireg*/);
194 unsigned SrcReg = Src.getReg();
197 TargetRegisterInfo::isVirtualRegister(SrcReg)) {
201 PeepholeMap[DstReg] = SrcReg;
    [all...]
HexagonCopyToCombine.cpp 122 unsigned SrcReg = MI->getOperand(1).getReg();
124 Hexagon::IntRegsRegClass.contains(SrcReg);
  /external/llvm/lib/Target/R600/
SIFixSGPRCopies.cpp 182 unsigned SrcReg = Copy.getOperand(1).getReg();
187 if (!TargetRegisterInfo::isVirtualRegister(SrcReg) ||
189 MRI.getRegClass(SrcReg) == &AMDGPU::VReg_1RegClass)
192 SrcRC = TRI->getSubRegClass(MRI.getRegClass(SrcReg), SrcSubReg);
  /external/llvm/lib/Target/Sparc/
SparcRegisterInfo.cpp 178 unsigned SrcReg = MI.getOperand(2).getReg();
179 unsigned SrcEvenReg = getSubReg(SrcReg, SP::sub_even64);
180 unsigned SrcOddReg = getSubReg(SrcReg, SP::sub_odd64);
  /external/chromium_org/third_party/mesa/src/src/mesa/main/
atifragshader.h 55 struct atifragshader_src_register SrcReg[2][3];
  /external/mesa3d/src/mesa/main/
atifragshader.h 55 struct atifragshader_src_register SrcReg[2][3];
  /external/chromium_org/third_party/mesa/src/src/gallium/drivers/r300/compiler/
radeon_dataflow_deadcode.c 43 unsigned char SrcReg[3];
186 unsigned int newsrcmask = srcmasks[src] & ~insts->SrcReg[src];
187 insts->SrcReg[src] |= newsrcmask;
191 refmask |= 1 << GET_SWZ(inst->U.I.SrcReg[src].Swizzle, chan);
200 mark_used(s, inst->U.I.SrcReg[src].File, inst->U.I.SrcReg[src].Index, refmask);
202 if (inst->U.I.SrcReg[src].RelAddr)
260 ptr->U.I.SrcReg[src].File,
261 ptr->U.I.SrcReg[src].Index,
353 SET_SWZ(inst->U.I.SrcReg[src].Swizzle, chan, RC_SWIZZLE_UNUSED)
    [all...]
radeon_program.h 66 struct rc_src_register SrcReg[2];
78 struct rc_src_register SrcReg[3];
  /external/llvm/lib/CodeGen/SelectionDAG/
FunctionLoweringInfo.cpp 345 unsigned SrcReg = ValueMap[V];
346 if (!TargetRegisterInfo::isVirtualRegister(SrcReg)) {
350 const LiveOutInfo *SrcLOI = GetLiveOutRegInfo(SrcReg, BitWidth);
382 unsigned SrcReg = ValueMap[V];
383 if (!TargetRegisterInfo::isVirtualRegister(SrcReg)) {
387 const LiveOutInfo *SrcLOI = GetLiveOutRegInfo(SrcReg, BitWidth);
  /external/llvm/lib/Target/ARM/
MLxExpansionPass.cpp 158 unsigned SrcReg = DefMI->getOperand(i).getReg();
159 if (TargetRegisterInfo::isVirtualRegister(SrcReg)) {
160 DefMI = MRI->getVRegDef(SrcReg);
Thumb2ITBlockPass.cpp 120 unsigned SrcReg = MI->getOperand(1).getReg();
123 if (Uses.count(DstReg) || Defs.count(SrcReg))
  /external/llvm/lib/Target/Mips/
MipsFastISel.cpp 74 bool EmitStore(MVT VT, unsigned SrcReg, Address &Addr,
106 MachineInstrBuilder EmitInstStore(unsigned Opc, unsigned SrcReg,
108 return EmitInst(Opc).addReg(SrcReg).addReg(MemReg).addImm(MemOffset);
214 bool MipsFastISel::EmitStore(MVT VT, unsigned SrcReg, Address &Addr,
239 EmitInstStore(Opc, SrcReg, Addr.Base.Reg, Addr.Offset);
267 unsigned SrcReg = 0;
279 SrcReg = getRegForValue(Op0);
280 if (SrcReg == 0)
288 if (!EmitStore(VT, SrcReg, Addr, cast<StoreInst>(I)->getAlignment()))
MipsOptimizePICCall.cpp 134 unsigned SrcReg = I->getOperand(0).getReg();
135 unsigned DstReg = getRegTy(SrcReg, MF) == MVT::i32 ? Mips::T9 : Mips::T9_64;
137 .addReg(SrcReg);
  /external/llvm/lib/Target/SystemZ/
SystemZElimCompare.cpp 191 unsigned SrcReg = Compare->getOperand(0).getReg();
194 if (getRegReferences(MBBI, SrcReg))
328 unsigned SrcReg = Compare->getOperand(0).getReg();
337 if (resultTests(MI, SrcReg, SrcSubReg)) {
352 SrcRefs |= getRegReferences(MI, SrcReg);
381 unsigned SrcReg = Compare->getOperand(0).getReg();
386 if (MBBI->modifiesRegister(SrcReg, TRI) ||
413 // Clear any intervening kills of SrcReg and SrcReg2.
416 MBBI->clearRegisterKills(SrcReg, TRI);
  /external/mesa3d/src/gallium/drivers/r300/compiler/
radeon_dataflow_deadcode.c 43 unsigned char SrcReg[3];
186 unsigned int newsrcmask = srcmasks[src] & ~insts->SrcReg[src];
187 insts->SrcReg[src] |= newsrcmask;
191 refmask |= 1 << GET_SWZ(inst->U.I.SrcReg[src].Swizzle, chan);
200 mark_used(s, inst->U.I.SrcReg[src].File, inst->U.I.SrcReg[src].Index, refmask);
202 if (inst->U.I.SrcReg[src].RelAddr)
260 ptr->U.I.SrcReg[src].File,
261 ptr->U.I.SrcReg[src].Index,
353 SET_SWZ(inst->U.I.SrcReg[src].Swizzle, chan, RC_SWIZZLE_UNUSED)
    [all...]
radeon_program.h 66 struct rc_src_register SrcReg[2];
78 struct rc_src_register SrcReg[3];
  /external/chromium_org/third_party/mesa/src/src/mesa/program/
program_parser.h 127 struct asm_src_register SrcReg[3];
  /external/llvm/lib/Target/AArch64/
AArch64InstrInfo.cpp 448 unsigned SrcReg = Cond[2].getReg();
451 MRI.constrainRegClass(SrcReg, &AArch64::GPR64spRegClass);
453 .addReg(SrcReg)
457 MRI.constrainRegClass(SrcReg, &AArch64::GPR32spRegClass);
459 .addReg(SrcReg)
590 unsigned &SrcReg, unsigned &DstReg,
602 SrcReg = MI.getOperand(1).getReg();
610 /// in SrcReg and SrcReg2, and the value it compares against in CmpValue.
612 bool AArch64InstrInfo::analyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
631 SrcReg = MI->getOperand(1).getReg()
    [all...]

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