| /external/llvm/lib/Target/ARM/ |
| ARMSelectionDAGInfo.h | 26 case ISD::SHL: return ARM_AM::lsl;
|
| /dalvik/dexgen/src/com/android/dexgen/rop/code/ |
| RegOps.java | 115 public static final int SHL = 23;
336 case SHL: return "shl";
|
| DexTranslationAdvice.java | 81 case RegOps.SHL:
|
| /dalvik/dx/src/com/android/dx/rop/code/ |
| RegOps.java | 115 public static final int SHL = 23;
336 case SHL: return "shl";
|
| DexTranslationAdvice.java | 88 case RegOps.SHL:
|
| /external/dexmaker/src/dx/java/com/android/dx/rop/code/ |
| RegOps.java | 115 public static final int SHL = 23;
336 case SHL: return "shl";
|
| DexTranslationAdvice.java | 88 case RegOps.SHL:
|
| /external/chromium_org/third_party/libvpx/source/libvpx/build/make/ |
| ads2gas_apple.pl | 71 # Convert :SHL: to <<
72 s/:SHL:/ << /g;
|
| ads2gas.pl | 72 # Convert :SHL: to <<
73 s/:SHL:/ << /g;
|
| /external/chromium_org/third_party/opus/src/celt/ |
| fixed_c5x.h | 71 #define MULT16_32_Q15(a,b) ADD32(SHL(MULT16_16((a),SHR((b),16)),1), SHR(MULT16_16SU((a),(b)),15))
|
| fixed_generic.h | 46 #define MULT16_32_Q15(a,b) ADD32(SHL(MULT16_16((a),SHR((b),16)),1), SHR(MULT16_16SU((a),((b)&0x0000ffff)),15))
49 #define MULT32_32_Q31(a,b) ADD32(ADD32(SHL(MULT16_16(SHR((a),16),SHR((b),16)),1), SHR(MULT16_16SU(SHR((a),16),((b)&0x0000ffff)),15)), SHR(MULT16_16SU(SHR((b),16),((a)&0x0000ffff)),15))
83 #define SHL(a,shift) SHL32(a,shift)
|
| /external/libhevc/common/mips/ |
| ihevc_platform_macros.h | 55 #define SHL(x,y) (((y) < 32) ? ((x) << (y)) : 0)
|
| /external/libvpx/libvpx/build/make/ |
| ads2gas_apple.pl | 71 # Convert :SHL: to <<
72 s/:SHL:/ << /g;
|
| ads2gas.pl | 72 # Convert :SHL: to <<
73 s/:SHL:/ << /g;
|
| /external/llvm/lib/Target/X86/ |
| X86TargetTransformInfo.cpp | 208 { ISD::SHL, MVT::v4i32, 1 },
211 { ISD::SHL, MVT::v8i32, 1 },
214 { ISD::SHL, MVT::v2i64, 1 },
216 { ISD::SHL, MVT::v4i64, 1 },
219 { ISD::SHL, MVT::v32i8, 42 }, // cmpeqb sequence.
220 { ISD::SHL, MVT::v16i16, 16*10 }, // Scalarized.
242 if (ISD == ISD::SHL && LT.second == MVT::v16i16 &&
259 { ISD::SHL, MVT::v16i8, 1 }, // psllw.
260 { ISD::SHL, MVT::v8i16, 1 }, // psllw.
261 { ISD::SHL, MVT::v4i32, 1 }, // psll
[all...] |
| /external/libhevc/common/x86/ |
| ihevc_platform_macros.h | 56 #define SHL(x,y) (((y) < 32) ? ((x) << (y)) : 0)
|
| /external/libopus/celt/ |
| fixed_generic.h | 46 #define MULT16_32_Q15(a,b) ADD32(SHL(MULT16_16((a),SHR((b),16)),1), SHR(MULT16_16SU((a),((b)&0x0000ffff)),15))
49 #define MULT32_32_Q31(a,b) ADD32(ADD32(SHL(MULT16_16(SHR((a),16),SHR((b),16)),1), SHR(MULT16_16SU(SHR((a),16),((b)&0x0000ffff)),15)), SHR(MULT16_16SU(SHR((b),16),((a)&0x0000ffff)),15))
83 #define SHL(a,shift) SHL32(a,shift)
|
| /external/libhevc/common/arm/ |
| ihevc_platform_macros.h | 111 #define SHL(x,y) (((y) < 32) ? ((x) << (y)) : 0)
|
| /external/chromium_org/v8/src/ic/ |
| ic-state.cc | 234 GENERATE(Token::SHL, INT32, SMI, INT32, NO_OVERWRITE);
235 GENERATE(Token::SHL, INT32, SMI, INT32, OVERWRITE_RIGHT);
236 GENERATE(Token::SHL, INT32, SMI, SMI, NO_OVERWRITE);
237 GENERATE(Token::SHL, INT32, SMI, SMI, OVERWRITE_RIGHT);
238 GENERATE(Token::SHL, NUMBER, SMI, SMI, OVERWRITE_RIGHT);
239 GENERATE(Token::SHL, SMI, SMI, INT32, NO_OVERWRITE);
240 GENERATE(Token::SHL, SMI, SMI, INT32, OVERWRITE_LEFT);
241 GENERATE(Token::SHL, SMI, SMI, INT32, OVERWRITE_RIGHT);
242 GENERATE(Token::SHL, SMI, SMI, SMI, NO_OVERWRITE);
243 GENERATE(Token::SHL, SMI, SMI, SMI, OVERWRITE_LEFT)
[all...] |
| /external/chromium_org/v8/src/ |
| token.h | 77 T(SHL, "<<", 11) \
270 return (SHL <= op) && (op <= SHR);
|
| /external/chromium_org/third_party/mesa/src/src/gallium/auxiliary/tgsi/ |
| tgsi_opcode_tmp.h | 122 OP12(SHL)
|
| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 311 SHL, SRA, SRL, ROTL, ROTR,
375 /// SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.h | 64 /// SHL, SRA, SRL - Non-constant shifts.
65 SHL, SRA, SRL
|
| /external/mesa3d/src/gallium/auxiliary/tgsi/ |
| tgsi_opcode_tmp.h | 122 OP12(SHL)
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeIntegerTypes.cpp | 73 case ISD::SHL: Res = PromoteIntRes_SHL(N); break;
576 return DAG.getNode(ISD::SHL, SDLoc(N), Res.getValueType(), Res, Amt);
768 Part = DAG.getNode(ISD::SHL, dl, NVT, Part,
[all...] |
