/external/llvm/lib/Target/Mips/ |
MipsAnalyzeImmediate.cpp | 32 AddInstr(SeqLs, Inst(ADDiu, Imm & 0xffffULL)); 56 // A single ADDiu will do if RemSize <= 16. 58 AddInstr(SeqLs, Inst(ADDiu, MaskedImm)); 71 // instruction is an ADDiu or ORi. In that case, do not call GetInstSeqLsORi. 79 // Replace a ADDiu & SLL pair with a LUi. 81 // ADDiu 0x0111 86 // Check if the first two instructions are ADDiu and SLL and the shift amount 88 if ((Seq.size() < 2) || (Seq[0].Opc != ADDiu) || 92 // Sign-extend and shift operand of ADDiu and see if it still fits in 16-bit. 130 ADDiu = Mips::ADDiu [all...] |
MipsAnalyzeImmediate.h | 26 /// instruction in the sequence must be an ADDiu if LastInstrIsADDiu is 35 /// GetInstSeqLsADDiu - Get instruction sequences which end with an ADDiu to 50 /// ReplaceADDiuSLLWithLUi - Replace an ADDiu & SLL pair with a LUi. 58 unsigned ADDiu, ORi, SLL, LUi;
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MipsSERegisterInfo.cpp | 165 // (where n < 16) and doesn't, but does fit into 16-bits then use an ADDiu 168 unsigned ADDiu = Subtarget.isABI_N64() ? Mips::DADDiu : Mips::ADDiu; 176 BuildMI(MBB, II, DL, TII.get(ADDiu), Reg).addReg(FrameReg).addImm(Offset);
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MipsLongBranch.cpp | 278 // addiu $sp, $sp, -8 282 // addiu $at, $at, %lo($tgt - $baltgt) 287 // addiu $sp, $sp, 8 293 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP) 298 // LUi and ADDiu instructions create 32-bit offset of the target basic 307 // we replace LUi and ADDiu with pseudo instructions 310 // instructions to LUi and ADDiu in the MC layer, we will create 333 .append(BuildMI(*MF, DL, TII->get(Mips::ADDiu), Mips::SP) 337 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP) 443 BuildMI(MBB, I, DL, TII->get(Mips::ADDiu), Mips::V0 [all...] |
MipsMCInstLower.cpp | 202 lowerLongBranchADDiu(MI, OutMI, Mips::ADDiu,
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MipsSEISelDAGToDAG.cpp | 89 // Check if MI is "addiu $dst, $zero, 0" or "daddiu $dst, $zero, 0". 90 if ((MI.getOpcode() == Mips::ADDiu) && 166 // addiu $globalbasereg, $v0, %lo(__gnu_local_gp) 169 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0) 180 // addiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname))) 185 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V1) 196 // 1. addiu $2, $2, %lo(_gp_disp) 207 // the value instruction 1 (addiu) defines is valid when instruction 2 (addu) 318 // addiu $2, $2, %lo($CPI1_0) 702 // instructions (ADDiu, ORI and SLL) in that it does not have a registe [all...] |
MipsSEInstrInfo.cpp | 366 unsigned ADDiu = STI.isABI_N64() ? Mips::DADDiu : Mips::ADDiu; 369 BuildMI(MBB, I, DL, get(ADDiu), SP).addReg(SP).addImm(Amount); 399 // instructions (ADDiu, ORI and SLL) in that it does not have a register
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MipsFastISel.cpp | 375 unsigned Opc = Mips::ADDiu;
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MipsSEISelLowering.cpp | [all...] |
MipsISelLowering.cpp | 598 // addiu $reg2, $reg1, y-1 605 // addiu $reg2, $reg1, y-1 [all...] |
/external/llvm/lib/Target/Mips/MCTargetDesc/ |
MipsTargetStreamer.cpp | 542 // addiu $gp, $gp, %lo(__gnu_local_gp) 559 TmpInst.setOpcode(Mips::ADDiu); 617 // addiu $gp, $gp, %lo(%neg(%gp_rel(funcSym))) 618 Inst.setOpcode(Mips::ADDiu);
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/external/llvm/lib/Target/Mips/AsmParser/ |
MipsAsmParser.cpp | [all...] |