| /external/libhevc/decoder/arm/ |
| ihevcd_fmt_conv_420sp_to_rgba8888.s | 236 VQMOVUN.S16 D20,Q10
241 VZIP.8 D20,D21
250 VST1.32 D20,[R2]!
257 @//D14-D20 - TOALLY HAVE 16 VALUES
287 VQMOVUN.S16 D20,Q10
292 VZIP.8 D20,D21
301 VST1.32 D20,[R8]!
367 VQMOVUN.S16 D20,Q10
372 VZIP.8 D20,D21
381 VST1.32 D20,[R2]
[all...] |
| /external/llvm/test/MC/MachO/ |
| x86_32-symbols.s | 65 D20:
861 // CHECK: ('_string', 'D20')
|
| x86_64-symbols.s | 65 D20:
794 // CHECK: ('_string', 'D20')
|
| /art/runtime/arch/arm64/ |
| registers_arm64.h | 135 D20 = 20,
|
| context_arm64.cc | 132 fprs_[D20] = nullptr;
|
| /external/libhevc/common/arm/ |
| ihevc_sao_band_offset_chroma.s | 261 VCLE.U8 D20,D9,D29 @vcle_u8(band_table.val[0], vdup_n_u8(16))
262 VORR.U8 D9,D9,D20 @band_table.val[0] = vorr_u8(band_table.val[0], au1_cmp)
271 VCLE.U8 D20,D9,D29 @vcle_u8(band_table.val[0], vdup_n_u8(16))
272 VAND.U8 D9,D9,D20 @band_table.val[0] = vand_u8(band_table.val[0], au1_cmp)
305 VSUB.I8 D20,D18,D30 @vsub_u8(au1_cur_row_deint.val[1], band_pos_v)
318 VTBX.8 D18,{D9-D12},D20 @vtbx4_u8(au1_cur_row_deint.val[1], band_table_v, vsub_u8(au1_cur_row_deint.val[1], band_pos_v))
359 VSUB.I8 D20,D18,D30 @vsub_u8(au1_cur_row_deint.val[1], band_pos_v)
370 VTBX.8 D18,{D9-D12},D20 @vtbx4_u8(au1_cur_row_deint.val[1], band_table_v, vsub_u8(au1_cur_row_deint.val[1], band_pos_v))
|
| ihevc_sao_edge_offset_class3_chroma.s | 431 VMOVN.I16 D20,Q10 @I vmovn_s16(pi2_tmp_cur_row.val[0])
532 VLD1.8 D20,[r2] @edge_idx_tbl = vld1_s8(gi1_table_edge_idx)
536 VTBL.8 D18,{D20},D18 @III vtbl1_s8(edge_idx_tbl, vget_low_s8(edge_idx))
540 VTBL.8 D19,{D20},D19 @III vtbl1_s8(edge_idx_tbl, vget_high_s8(edge_idx))
585 VMOVN.I16 D20,Q10 @III vmovn_s16(pi2_tmp_cur_row.val[0])
[all...] |
| ihevc_sao_band_offset_luma.s | 209 VSUB.I8 D20,D19,D31 @vsub_u8(au1_cur_row, band_pos)
211 VTBX.8 D19,{D1-D4},D20 @vtbx4_u8(au1_cur_row, band_table, vsub_u8(au1_cur_row, band_pos))
|
| ihevc_sao_edge_offset_class1.s | 198 VMOVN.I16 D20,Q10 @vmovn_s16(pi2_tmp_cur_row.val[0])
323 VMOVN.I16 D20,Q10 @vmovn_s16(pi2_tmp_cur_row.val[0])
330 VST1.8 {D20},[r10],r1 @vst1q_u8(pu1_src_cpy, pu1_cur_row)
|
| ihevc_sao_edge_offset_class1_chroma.s | 209 VMOVN.I16 D20,Q10 @vmovn_s16(pi2_tmp_cur_row.val[0])
350 VMOVN.I16 D20,Q10 @vmovn_s16(pi2_tmp_cur_row.val[0])
361 VST1.8 {D20},[r10],r1 @vst1q_u8(pu1_src_cpy, pu1_cur_row)
|
| ihevc_sao_edge_offset_class2_chroma.s | 440 VMOVN.I16 D20,Q10 @I vmovn_s16(pi2_tmp_cur_row.val[0])
538 VLD1.8 D20,[r2] @edge_idx_tbl = vld1_s8(gi1_table_edge_idx)
545 VTBL.8 D18,{D20},D18 @III vtbl1_s8(edge_idx_tbl, vget_low_s8(edge_idx))
548 VTBL.8 D19,{D20},D19 @III vtbl1_s8(edge_idx_tbl, vget_high_s8(edge_idx))
588 VMOVN.I16 D20,Q10 @III vmovn_s16(pi2_tmp_cur_row.val[0])
[all...] |
| /external/chromium_org/third_party/openmax_dl/dl/sp/src/arm/neon/ |
| armSP_FFT_CToC_FC32_Radix8_fs_unsafe_s.S | 100 #define dUr4 D20.F32
135 #define dVr5 D20.F32
152 #define dYr4 D20.F32
|
| armSP_FFT_CToC_SC16_Radix8_fs_unsafe_s.S | 111 #define dUr4 D20.S16
147 #define dVr5 D20.S16
168 #define dYr4 D20.S16
|
| armSP_FFT_CToC_SC32_Radix8_fs_unsafe_s.S | 110 #define dUr4 D20.S32
146 #define dVr5 D20.S32
165 #define dYr4 D20.S32
|
| armSP_FFT_CToC_FC32_Radix4_fs_unsafe_s.S | 99 #define dZr2 D20.F32
|
| armSP_FFT_CToC_SC16_Radix4_fs_unsafe_s.S | 99 #define dZr2 D20.S16
|
| omxSP_FFTInv_CCSToR_F32_Sfs_s.S | 122 #define dzero D20.F32
|
| armSP_FFT_CToC_FC32_Radix4_ls_unsafe_s.S | 92 #define dYr2 D20.F32
106 #define qT3 d20.f32
|
| armSP_FFT_CToC_FC32_Radix4_unsafe_s.S | 103 #define dZr0 D20.F32
|
| armSP_FFT_CToC_SC16_Radix4_ls_unsafe_s.S | 127 #define dYr2 D20.S16
|
| armSP_FFT_CToC_SC16_Radix4_unsafe_s.S | 111 #define dZr0 D20.S16
|
| armSP_FFT_CToC_SC32_Radix4_fs_unsafe_s.S | 107 #define dZr2 D20.S32
|
| omxSP_FFTInv_CCSToR_S32_Sfs_s.S | 139 #define dzero D20.S32
|
| /art/compiler/utils/arm/ |
| constants_arm.h | 83 D20 = 20,
|
| /art/compiler/utils/arm64/ |
| managed_register_arm64_test.cc | 193 reg = Arm64ManagedRegister::FromDRegister(D20);
201 EXPECT_EQ(D20, reg.AsDRegister());
203 EXPECT_TRUE(reg.Equals(Arm64ManagedRegister::FromDRegister(D20)));
586 EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromDRegister(D20)));
609 EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromDRegister(D20)));
[all...] |
