/external/chromium_org/v8/src/ |
natives.h | 20 CORE, EXPERIMENTAL, D8, TEST
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natives-external.cc | 194 template class NativesCollection<D8>;
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/external/clang/test/CXX/special/class.copy/ |
p23-cxx11.cpp | 125 struct D8 { 140 template struct CopyAssign<D8>; // expected-note {{here}} 141 template struct MoveAssign<D8>; // expected-note {{here}} 142 template struct MoveOrCopyAssign<D8>; // expected-note {{here}}
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/art/compiler/utils/mips/ |
constants_mips.h | 40 D8 = 8,
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/external/llvm/test/MC/MachO/ |
x86_32-symbols.s | 29 D8: 765 // CHECK: ('_string', 'D8')
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x86_64-symbols.s | 29 D8: 730 // CHECK: ('_string', 'D8')
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/external/llvm/unittests/Support/ |
AlignOfTest.cpp | 68 struct D8 : S1, D4, D5 { double x[2]; }; 124 [AlignOf<D8>::Alignment > 0] 165 EXPECT_LE(alignOf<S1>(), alignOf<D8>()); 243 EXPECT_EQ(alignOf<D8>(), alignOf<AlignedCharArrayUnion<D8> >()); 298 EXPECT_EQ(sizeof(D8), sizeof(AlignedCharArrayUnion<D8>));
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/art/runtime/arch/arm64/ |
registers_arm64.h | 123 D8 = 8,
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quick_method_frame_info_arm64.h | 58 (1 << art::arm64::D8) | (1 << art::arm64::D9) | (1 << art::arm64::D10) |
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/external/chromium_org/third_party/openmax_dl/dl/sp/src/arm/neon/ |
armSP_FFT_CToC_FC32_Radix2_unsafe_s.S | 79 #define dY2 D8.F32
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armSP_FFT_CToC_SC16_Radix2_ls_unsafe_s.S | 88 #define dYr1 D8.S16
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armSP_FFT_CToC_SC16_Radix2_ps_unsafe_s.S | 84 #define dY2 D8.S16
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armSP_FFT_CToC_SC16_Radix2_unsafe_s.S | 85 #define dY2 D8.S16
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armSP_FFT_CToC_SC32_Radix2_unsafe_s.S | 87 #define dY2 D8.S32
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armSP_FFT_CToC_SC16_Radix4_ls_unsafe_s.S | 103 #define dW1rS32 D8.S32 110 #define dW1r D8.S16
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armSP_FFTInv_CCSToR_F32_preTwiddleRadix2_unsafe_s.S | 101 #define dT0 D8.F32
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/external/libhevc/common/arm/ |
ihevc_sao_edge_offset_class0_chroma.s | 126 VMOV.8 D8[0],r12 @vsetq_lane_s8(pu1_avail[0], au1_mask, 0) 127 VMOV.8 D8[1],r12 @vsetq_lane_s8(pu1_avail[0], au1_mask, 1) 132 VMOV.16 D8[0],r12 @au1_mask = vsetq_lane_s8(-1, au1_mask, 0) 292 VMOV.8 D8[0],r12 @vsetq_lane_s8(pu1_avail[0], au1_mask, 0) 293 VMOV.8 D8[1],r12 @vsetq_lane_s8(pu1_avail[0], au1_mask, 0) 298 VMOV.16 D8[0],r12 @au1_mask = vsetq_lane_s8(-1, au1_mask, 0) 302 VMOV.8 D8[6],r12 @au1_mask = vsetq_lane_s8(pu1_avail[1], au1_mask, 15) 303 VMOV.8 D8[7],r12 @au1_mask = vsetq_lane_s8(pu1_avail[1], au1_mask, 15)
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ihevc_sao_edge_offset_class1_chroma.s | 117 VLD1.8 D8,[r7] @offset_tbl_v = vld1_s8(pi1_sao_offset_v) 184 VTBL.8 D13,{D8},D13 203 VTBL.8 D25,{D8},D23 251 VTBL.8 D25,{D8},D23 334 VTBL.8 D13,{D8},D13 352 VTBL.8 D25,{D8},D23 387 VTBL.8 D25,{D8},D23
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ihevc_sao_band_offset_chroma.s | 133 VADD.I8 D8,D4,D31 @band_table_u.val[3] = vadd_u8(band_table_u.val[3], sao_band_pos_u) 151 VADD.I8 D4,D8,D26 @band_table_u.val[3] = vadd_u8(band_table_u.val[3], vdup_n_u8(pi1_sao_offset_u[4])) 293 VSUB.I8 D8,D6,D30 @vsub_u8(au1_cur_row_deint.val[1], band_pos_v) 301 VTBX.8 D6,{D9-D12},D8 @vtbx4_u8(au1_cur_row_deint.val[1], band_table_v, vsub_u8(au1_cur_row_deint.val[1], band_pos_v)) 347 VSUB.I8 D8,D6,D30 @vsub_u8(au1_cur_row_deint.val[1], band_pos_v) 352 VTBX.8 D6,{D9-D12},D8 @vtbx4_u8(au1_cur_row_deint.val[1], band_table_v, vsub_u8(au1_cur_row_deint.val[1], band_pos_v))
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ihevc_sao_edge_offset_class0.s | 122 VMOV.8 D8[0],r12 @vsetq_lane_s8(pu1_avail[0], au1_mask, 0) 127 VMOV.8 D8[0],r12 @au1_mask = vsetq_lane_s8(-1, au1_mask, 0) 274 VMOV.8 D8[0],r12 @vsetq_lane_s8(pu1_avail[0], au1_mask, 0) 279 VMOV.8 D8[0],r12 @au1_mask = vsetq_lane_s8(-1, au1_mask, 0) 286 VMOV.8 D8[7],r11 @au1_mask = vsetq_lane_s8(pu1_avail[1], au1_mask, 15)
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ihevc_sao_band_offset_luma.s | 127 VADD.I8 D8,D4,D31 @band_table.val[3] = vadd_u8(band_table.val[3], band_pos) 138 VADD.I8 D4,D8,D26 @band_table.val[3] = vadd_u8(band_table.val[3], vdup_n_u8(pi1_sao_offset[4]))
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/external/llvm/lib/Target/ARM/ |
ARMBaseRegisterInfo.h | 68 case D11: case D10: case D9: case D8:
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ARMFrameLowering.cpp | 247 if (Reg == ARM::D8) 249 if (Reg < ARM::D8 || Reg >= ARM::D8 + AFI->getNumAlignedDPRCS2Regs()) 483 (Reg < ARM::D8 || Reg >= ARM::D8 + AFI->getNumAlignedDPRCS2Regs())) { 820 if (Reg >= ARM::D8 && Reg < ARM::D8 + NumAlignedDPRCS2Regs) [all...] |
/external/libhevc/decoder/arm/ |
ihevcd_fmt_conv_420sp_to_rgba8888.s | 204 VQSHRN.S32 D8,Q4,#13 @//D8 = (U-128)*C4>>13 4 16-BIT VALUES 335 VQSHRN.S32 D8,Q4,#13 @//D8 = (U-128)*C4>>13 4 16-BIT VALUES
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/art/compiler/utils/arm/ |
constants_arm.h | 68 D8 = 8,
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