| /external/llvm/include/llvm/MC/ |
| MCInstrItineraries.h | 195 /// index DefIdx can be bypassed when it's read by an instruction of
197 bool hasPipelineForwarding(unsigned DefClass, unsigned DefIdx,
201 if ((FirstDefIdx + DefIdx) >= LastDefIdx)
203 if (Forwardings[FirstDefIdx + DefIdx] == 0)
211 return Forwardings[FirstDefIdx + DefIdx] ==
218 int getOperandLatency(unsigned DefClass, unsigned DefIdx,
223 int DefCycle = getOperandCycle(DefClass, DefIdx);
233 hasPipelineForwarding(DefClass, DefIdx, UseClass, UseIdx))
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| MCSubtargetInfo.h | 103 unsigned DefIdx) const {
104 assert(DefIdx < SC->NumWriteLatencyEntries &&
105 "MachineModel does not specify a WriteResource for DefIdx");
107 return &WriteLatencyTable[SC->WriteLatencyIdx + DefIdx];
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| /external/llvm/lib/CodeGen/ |
| TargetSchedule.cpp | 129 unsigned DefIdx = 0;
133 ++DefIdx;
135 return DefIdx;
189 unsigned DefIdx = findDefIdx(DefMI, DefOperIdx);
190 if (DefIdx < SCDesc->NumWriteLatencyEntries) {
193 STI->getWriteLatencyEntry(SCDesc, DefIdx);
209 // If DefIdx does not exist in the model (e.g. implicit defs), then return
217 ss << "DefIdx " << DefIdx << " exceeds machine model writes for "
241 for (unsigned DefIdx = 0, DefEnd = SCDesc->NumWriteLatencyEntries
[all...] |
| PeepholeOptimizer.cpp | 166 unsigned DefIdx;
205 /// at the operand index \p DefIdx.
212 ValueTracker(const MachineInstr &MI, unsigned DefIdx, unsigned DefSubReg,
215 : Def(&MI), DefIdx(DefIdx), DefSubReg(DefSubReg),
217 assert(Def->getOperand(DefIdx).isDef() &&
218 Def->getOperand(DefIdx).isReg() &&
221 Reg = Def->getOperand(DefIdx).getReg();
462 unsigned SrcIdx, DefIdx;
465 SrcIdx, DefIdx) != nullptr
[all...] |
| LiveRangeEdit.cpp | 128 SlotIndex DefIdx;
130 DefIdx = LIS.getInstructionIndex(RM.OrigMI);
132 DefIdx = RM.ParentVNI->def;
133 RM.OrigMI = LIS.getInstructionFromIndex(DefIdx);
142 if (!allUsesAvailableAt(RM.OrigMI, DefIdx, UseIdx))
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| TargetInstrInfo.cpp | 702 SDNode *DefNode, unsigned DefIdx,
712 return ItinData->getOperandCycle(DefClass, DefIdx);
714 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
778 unsigned DefIdx) const {
783 int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
791 const MachineInstr *DefMI, unsigned DefIdx,
795 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
824 /// to call getOperandLatency(). For most subtargets, we don't need DefIdx or
828 const MachineInstr *DefMI, unsigned DefIdx,
839 OperLatency = getOperandLatency(ItinData, DefMI, DefIdx, UseMI, UseIdx)
[all...] |
| LiveRangeCalc.cpp | 90 unsigned DefIdx;
94 } else if (MI->isRegTiedToDefOperand(OpNo, &DefIdx)) {
97 if (MI->getOperand(DefIdx).isEarlyClobber())
|
| MachineVerifier.cpp | 888 unsigned DefIdx;
890 MI->isRegTiedToDefOperand(MONum, &DefIdx) &&
891 Reg != MI->getOperand(DefIdx).getReg())
[all...] |
| MachineInstr.cpp | 720 int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO);
721 if (DefIdx != -1)
722 tieOperands(DefIdx, OpNo);
[all...] |
| RegisterCoalescer.cpp | 597 int DefIdx = DefMI->findRegisterDefOperandIdx(IntA.reg);
598 assert(DefIdx != -1);
600 if (!DefMI->isRegTiedToUseOperand(DefIdx, &UseOpIdx))
699 SlotIndex DefIdx = UseIdx.getRegSlot();
700 VNInfo *DVNI = IntB.getVNInfoAt(DefIdx);
703 DEBUG(dbgs() << "\t\tnoop: " << DefIdx << '\t' << *UseMI);
704 assert(DVNI->def == DefIdx);
[all...] |
| InlineSpiller.cpp | [all...] |
| RegAllocFast.cpp | 736 unsigned DefIdx = 0;
737 if (!MI->isRegTiedToDefOperand(i, &DefIdx)) continue;
739 << DefIdx << ".\n");
[all...] |
| MachineLICM.cpp | 201 bool HasHighOperandLatency(MachineInstr &MI, unsigned DefIdx,
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| ScheduleDAGSDNodes.h | 136 unsigned DefIdx;
154 return DefIdx-1;
|
| ScheduleDAGSDNodes.cpp | 554 DefIdx = 0;
560 : SchedDAG(SD), Node(SU->getNode()), DefIdx(0), NodeNumDefs(0) {
568 for (;DefIdx < NodeNumDefs; ++DefIdx) {
569 if (!Node->hasAnyUseOfValue(DefIdx))
571 ValueType = Node->getSimpleValueType(DefIdx);
572 ++DefIdx;
634 unsigned DefIdx = Use->getOperand(OpIdx).getResNo();
638 int Latency = TII->getOperandLatency(InstrItins, Def, DefIdx, Use, OpIdx);
[all...] |
| InstrEmitter.cpp | [all...] |
| /external/llvm/include/llvm/CodeGen/ |
| TargetSchedule.h | 174 unsigned computeOutputLatency(const MachineInstr *DefMI, unsigned DefIdx,
|
| MachineInstr.h | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMBaseInstrInfo.h | 216 const MachineInstr *DefMI, unsigned DefIdx,
220 SDNode *DefNode, unsigned DefIdx,
248 unsigned DefIdx, unsigned DefAlign) const;
252 unsigned DefIdx, unsigned DefAlign) const;
263 unsigned DefIdx, unsigned DefAlign,
278 const MachineInstr *DefMI, unsigned DefIdx,
283 unsigned DefIdx) const override;
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| ARMBaseInstrInfo.cpp | [all...] |
| /external/llvm/lib/MC/MCDisassembler/ |
| Disassembler.cpp | 225 for (unsigned DefIdx = 0, DefEnd = SCDesc->NumWriteLatencyEntries;
226 DefIdx != DefEnd; ++DefIdx) {
229 DefIdx);
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCInstrInfo.h | 99 const MachineInstr *DefMI, unsigned DefIdx,
103 SDNode *DefNode, unsigned DefIdx,
105 return PPCGenInstrInfo::getOperandLatency(ItinData, DefNode, DefIdx,
|
| PPCInstrInfo.cpp | 109 const MachineInstr *DefMI, unsigned DefIdx,
112 int Latency = PPCGenInstrInfo::getOperandLatency(ItinData, DefMI, DefIdx,
115 const MachineOperand &DefMO = DefMI->getOperand(DefIdx);
[all...] |
| /external/llvm/include/llvm/Target/ |
| TargetInstrInfo.h | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86InstrInfo.h | 419 const MachineInstr *DefMI, unsigned DefIdx,
|
