| /art/test/065-mismatched-implements/src/ |
| Defs.java | 17 public interface Defs {
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| Base.java | 17 public class Base implements Defs {
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| /art/test/066-mismatched-super/src/ |
| Base.java | 17 public class Base extends Defs {
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| Defs.java | 17 public abstract class Defs {
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| /art/test/066-mismatched-super/src2/ |
| Defs.java | 17 public interface Defs {
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| /art/test/065-mismatched-implements/src2/ |
| Defs.java | 17 public abstract class Defs {
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| /external/chromium_org/third_party/skia/src/svg/ |
| SkSVGDefs.h | 16 DECLARE_SVG_INFO(Defs);
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| SkSVGDefs.cpp | 12 DEFINE_SVG_NO_INFO(Defs)
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| /external/llvm/lib/CodeGen/ |
| LivePhysRegs.cpp | 35 /// Remove Defs, add uses. This is the recommended way of calculating liveness.
62 /// killed-uses, add defs. This is the not recommended way, because it depends
66 SmallVector<unsigned, 4> Defs;
75 Defs.push_back(Reg);
86 // Add defs to the set.
87 for (unsigned i = 0, e = Defs.size(); i != e; ++i)
88 addReg(Defs[i]);
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| MachineCopyPropagation.cpp | 72 const DestList& Defs = SI->second;
73 for (DestList::const_iterator I = Defs.begin(), E = Defs.end();
239 SmallVector<unsigned, 2> Defs;
256 Defs.push_back(Reg);
299 for (unsigned i = 0, e = Defs.size(); i != e; ++i) {
300 unsigned Reg = Defs[i];
314 // If MBB doesn't have successors, delete the copies whose defs are not used.
315 // If MBB does have successors, then conservative assume the defs are live-out
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| MachineInstrBundle.cpp | 98 /// bundle, and it copies externally visible defs and uses to the BUNDLE
122 SmallVector<MachineOperand*, 4> Defs;
129 Defs.push_back(&MO);
154 for (unsigned i = 0, e = Defs.size(); i != e; ++i) {
155 MachineOperand &MO = *Defs[i];
182 Defs.clear();
264 // Both defs and uses can read virtual registers.
271 // Only defs can write.
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| LiveVariables.cpp | 229 /// implicit defs to a machine instruction if there was an earlier def of its
444 SmallVectorImpl<unsigned> &Defs) {
483 Defs.push_back(Reg); // Remember this def.
487 SmallVectorImpl<unsigned> &Defs) {
488 while (!Defs.empty()) {
489 unsigned Reg = Defs.back();
490 Defs.pop_back();
534 SmallVector<unsigned, 4> Defs;
539 HandlePhysRegDef(*II, nullptr, Defs);
596 // Process all defs
[all...] |
| RegisterPressure.cpp | 308 /// Collect this instruction's unique uses and defs into SmallVectors for
309 /// processing defs and uses in order.
319 SmallVector<unsigned, 8> Defs;
338 pushRegUnits(MO.getReg(), Defs);
365 // Remove redundant physreg dead defs.
368 std::bind1st(std::ptr_fun(containsReg), RegOpers.Defs));
415 for (unsigned i = 0, e = RegOpers.Defs.size(); i != e; ++i)
416 PDiff.addPressureChange(RegOpers.Defs[i], true, MRI);
494 // Boost pressure for all dead defs together.
498 // Kill liveness at live defs
[all...] |
| MachineLICM.cpp | 462 // FIXME: For now, avoid instructions with multiple defs, unless
470 // register, then this is not safe. Two defs is indicated by setting a
507 // Walk the entire region, count number of defs for each register, and
805 // defs as well. This happens whenever the preheader is created by splitting
848 SmallVector<unsigned, 4> Defs;
859 Defs.push_back(Reg);
[all...] |
| LiveDebugVariables.cpp | 239 /// points, and add defs if possible.
243 /// @param NewDefs Append (Idx, LocNo) of inserted defs here.
609 // Try to add defs of the copied values for each kill point.
639 SmallVector<std::pair<SlotIndex, unsigned>, 16> Defs;
641 // Collect all defs to be extended (Skipping undefs).
644 Defs.push_back(std::make_pair(I.start(), I.value()));
646 // Extend all defs, and possibly add new ones along the way.
647 for (unsigned i = 0; i != Defs.size(); ++i) {
648 SlotIndex Idx = Defs[i].first;
649 unsigned LocNo = Defs[i].second
[all...] |
| ScheduleDAGInstrs.cpp | 207 /// the exit SU to the register defs and use list. This is because we want to
219 // If it's a call or a barrier, add dependencies on the defs and uses of
276 // Set the hasPhysRegDefs only for physreg defs that have a use within
308 if (!Defs.contains(*Alias))
310 for (Reg2SUnitsMap::iterator I = Defs.find(*Alias); I != Defs.end(); ++I) {
347 Defs.eraseAll(Reg);
354 Reg2SUnitsMap::RangePair P = Defs.equal_range(Reg);
361 I = Defs.erase(I);
365 // Defs are pushed in the order they are visited and never reordered
[all...] |
| /external/llvm/lib/Target/ARM/ |
| Thumb2ITBlockPass.cpp | 46 SmallSet<unsigned, 4> &Defs,
57 SmallSet<unsigned, 4> &Defs,
87 Defs.insert(*Subreg);
108 SmallSet<unsigned, 4> &Defs,
123 if (Uses.count(DstReg) || Defs.count(SrcReg))
165 SmallSet<unsigned, 4> Defs;
178 Defs.clear();
180 TrackDefUses(MI, Defs, Uses, TRI);
221 MoveCopyOutOfITBlock(NMI, CC, OCC, Defs, Uses)) {
230 TrackDefUses(NMI, Defs, Uses, TRI)
[all...] |
| A15SDOptimizer.cpp | 407 SmallVector<unsigned, 8> Defs;
418 Defs.push_back(MO.getReg());
420 return Defs;
614 SmallVector<unsigned, 8> Defs = getReadDPRs(MI);
617 for (SmallVectorImpl<unsigned>::iterator I = Defs.begin(), E = Defs.end();
621 // we can end up with multiple defs of this DPR.
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| /external/llvm/utils/TableGen/ |
| CTagsEmitter.cpp | 73 const std::map<std::string, Record *> &Defs = Records.getDefs();
76 Tags.reserve(Classes.size() + Defs.size());
81 for (std::map<std::string, Record *>::const_iterator I = Defs.begin(),
82 E = Defs.end();
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| InstrInfoEmitter.cpp | 360 // Emit all of the instruction's implicit uses and defs.
368 std::vector<Record*> Defs = Inst->getValueAsListOfDefs("Defs");
369 if (!Defs.empty()) {
370 unsigned &IL = EmittedLists[Defs];
371 if (!IL) PrintDefList(Defs, IL = ++ListNumber, OS);
523 // Emit the implicit uses and defs lists...
530 std::vector<Record*> DefList = Inst.TheDef->getValueAsListOfDefs("Defs");
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| /external/llvm/lib/Target/Mips/ |
| MipsDelaySlotFiller.cpp | 75 /// This function sets all caller-saved registers in Defs.
78 /// This function sets all unallocatable registers in Defs.
96 BitVector Defs, Uses;
150 /// Update Defs and Uses. Return true if there exist dependences that
152 /// Defs.
160 SmallPtrSet<ValueType, 4> Uses, Defs;
289 : TRI(*TM.getRegisterInfo()), Defs(TRI.getNumRegs(), false),
296 // If MI is a call, add RA to Defs to prevent users of RA from going into
299 Defs.set(Mips::RA);
305 Defs.reset(Mips::AT)
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| LiveVariables.h | 160 SmallVectorImpl<unsigned> &Defs);
161 void UpdatePhysRegDefs(MachineInstr *MI, SmallVectorImpl<unsigned> &Defs);
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| ScheduleDAGInstrs.h | 82 /// Live Intervals provides reaching defs in preRA scheduling.
129 /// Defs, Uses - Remember where defs and uses of each register are as we
133 Reg2SUnitsMap Defs;
140 /// unknown store, as we iterate. As with Defs and Uses, this is here
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| /external/clang/utils/TableGen/ |
| NeonEmitter.cpp | 491 void genBuiltinsDef(raw_ostream &OS, SmallVectorImpl<Intrinsic *> &Defs);
493 SmallVectorImpl<Intrinsic *> &Defs);
495 SmallVectorImpl<Intrinsic *> &Defs);
[all...] |
| /external/clang/include/clang/Sema/ |
| MultiplexExternalSemaSource.h | 246 void ReadTentativeDefinitions(SmallVectorImpl<VarDecl*> &Defs) override;
|
