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    Searched refs:GPR32RegClass (Results 1 - 15 of 15) sorted by null

  /external/llvm/lib/Target/Mips/
MipsFastISel.cpp 163 ResultReg = createResultReg(&Mips::GPR32RegClass);
168 ResultReg = createResultReg(&Mips::GPR32RegClass);
173 ResultReg = createResultReg(&Mips::GPR32RegClass);
327 unsigned TempReg = Materialize32BitInt(Imm, &Mips::GPR32RegClass);
333 unsigned TempReg1 = Materialize32BitInt(Imm >> 32, &Mips::GPR32RegClass);
335 Materialize32BitInt(Imm & 0xFFFFFFFF, &Mips::GPR32RegClass);
346 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
360 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
MipsMachineFunction.cpp 89 (const TargetRegisterClass*)&Mips::GPR32RegClass;
110 &Mips::GPR64RegClass : &Mips::GPR32RegClass;
MipsSERegisterInfo.cpp 60 return &Mips::GPR32RegClass;
170 Subtarget.isABI_N64() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
MipsSEInstrInfo.cpp 89 if (Mips::GPR32RegClass.contains(DestReg)) { // Copy to CPU Reg.
90 if (Mips::GPR32RegClass.contains(SrcReg)) {
117 else if (Mips::GPR32RegClass.contains(SrcReg)) { // Copy from CPU Reg.
193 if (Mips::GPR32RegClass.hasSubClassEq(RC))
234 if (Mips::GPR32RegClass.hasSubClassEq(RC))
389 &Mips::GPR64RegClass : &Mips::GPR32RegClass;
MipsRegisterInfo.cpp 53 return Subtarget.isABI_N64() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
MipsSEFrameLowering.cpp 358 &Mips::GPR64RegClass : &Mips::GPR32RegClass;
424 &Mips::GPR64RegClass : &Mips::GPR32RegClass;
532 &Mips::GPR64RegClass : &Mips::GPR32RegClass;
546 &Mips::GPR64RegClass : &Mips::GPR32RegClass;
MipsSubtarget.cpp 186 : &Mips::GPR32RegClass);
Mips16InstrInfo.cpp 71 Mips::GPR32RegClass.contains(SrcReg))
73 else if (Mips::GPR32RegClass.contains(DestReg) &&
MipsAsmPrinter.cpp 254 unsigned CPURegSize = Mips::GPR32RegClass.getSize();
264 if (Mips::GPR32RegClass.contains(Reg))
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MipsSEISelDAGToDAG.cpp 140 RC = (const TargetRegisterClass*)&Mips::GPR32RegClass;
MipsSEISelLowering.cpp 40 addRegisterClass(MVT::i32, &Mips::GPR32RegClass);
    [all...]
MipsISelLowering.cpp     [all...]
  /external/llvm/lib/Target/AArch64/
AArch64FastISel.cpp 534 RC = &AArch64::GPR32RegClass;
539 RC = &AArch64::GPR32RegClass;
544 RC = &AArch64::GPR32RegClass;
585 MRI.constrainRegClass(ResultReg, &AArch64::GPR32RegClass);
674 MRI.constrainRegClass(SrcReg, &AArch64::GPR32RegClass);
798 MRI.constrainRegClass(CondReg, &AArch64::GPR32RegClass);
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AArch64InstrInfo.cpp 501 } else if (MRI.constrainRegClass(DstReg, &AArch64::GPR32RegClass)) {
502 RC = &AArch64::GPR32RegClass;
1002 return (AArch64::GPR32RegClass.contains(DstReg) ||
    [all...]
AArch64ISelLowering.cpp     [all...]

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