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    Searched refs:L2_CACHE_MISS_CYCLES (Results 1 - 4 of 4) sorted by null

/external/oprofile/events/mips/24K/
events	121 event:0x427 counters:1 um:zero minimum:500 name:L2_CACHE_MISS_CYCLES : 39-1 Cycles a L2 miss is outstanding, but not necessarily stalling the pipeline
/external/oprofile/events/mips/34K/
events	132 event:0x427 counters:1 um:zero minimum:500 name:L2_CACHE_MISS_CYCLES : 39-1 Cycles a L2 miss is outstanding, but not necessarily stalling the pipeline
/external/oprofile/events/mips/1004K/
events	141 event:0x427 counters:1 um:zero minimum:500 name:L2_CACHE_MISS_CYCLES : 39-1 Cycles a L2 miss is outstanding, but not necessarily stalling the pipeline
/external/oprofile/events/mips/74K/
events	123 event:0x41d counters:1,3 um:zero minimum:500 name:L2_CACHE_MISS_CYCLES : 29-1 Cycles a L2 miss is outstanding, but not necessarily stalling the pipeline

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