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    Searched refs:MCPhysReg (Results 1 - 25 of 63) sorted by null

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  /external/llvm/lib/CodeGen/
AllocationOrder.h 29 SmallVector<MCPhysReg, 16> Hints;
30 ArrayRef<MCPhysReg> Order;
43 ArrayRef<MCPhysReg> getOrder() const { return Order; }
RegisterClassInfo.cpp 51 const MCPhysReg *CSR = TRI->getCalleeSavedRegs(MF);
86 RCI.Order.reset(new MCPhysReg[NumRegs]);
89 SmallVector<MCPhysReg, 16> CSRAlias;
96 ArrayRef<MCPhysReg> RawOrder = RC->getRawAllocationOrder(*MF);
TargetRegisterInfo.cpp 133 ArrayRef<MCPhysReg> Order = RC->getRawAllocationOrder(MF);
265 ArrayRef<MCPhysReg> Order,
266 SmallVectorImpl<MCPhysReg> &Hints,
  /external/llvm/lib/Target/R600/
AMDGPURegisterInfo.h 32 static const MCPhysReg CalleeSavedReg;
53 const MCPhysReg* getCalleeSavedRegs(const MachineFunction *MF) const override;
AMDGPURegisterInfo.cpp 30 const MCPhysReg AMDGPURegisterInfo::CalleeSavedReg = AMDGPU::NoRegister;
32 const MCPhysReg*
  /external/llvm/include/llvm/CodeGen/
RegisterClassInfo.h 33 std::unique_ptr<MCPhysReg[]> Order;
39 operator ArrayRef<MCPhysReg>() const {
56 const MCPhysReg *CalleeSaved;
93 ArrayRef<MCPhysReg> getOrder(const TargetRegisterClass *RC) const {
CallingConvLower.h 300 unsigned getFirstUnallocated(const MCPhysReg *Regs, unsigned NumRegs) const {
327 unsigned AllocateReg(const MCPhysReg *Regs, unsigned NumRegs) {
364 unsigned AllocateReg(const MCPhysReg *Regs, const MCPhysReg *ShadowRegs,
397 const MCPhysReg *ShadowRegs, unsigned NumShadowRegs) {
  /external/llvm/lib/Target/MSP430/
MSP430RegisterInfo.h 29 const MCPhysReg *
MSP430RegisterInfo.cpp 38 const MCPhysReg*
42 static const MCPhysReg CalleeSavedRegs[] = {
47 static const MCPhysReg CalleeSavedRegsFP[] = {
52 static const MCPhysReg CalleeSavedRegsIntr[] = {
58 static const MCPhysReg CalleeSavedRegsIntrFP[] = {
  /external/llvm/lib/Target/XCore/
XCoreRegisterInfo.h 32 const MCPhysReg *
  /external/llvm/include/llvm/MC/
MCRegisterInfo.h 27 typedef uint16_t MCPhysReg;
32 typedef const MCPhysReg* iterator;
33 typedef const MCPhysReg* const_iterator;
162 const MCPhysReg (*RegUnitRoots)[2]; // Pointer to regunit root table.
163 const MCPhysReg *DiffLists; // Pointer to the difflists array
190 const MCPhysReg *List;
199 void init(MCPhysReg InitVal, const MCPhysReg *DiffList) {
209 MCPhysReg D = *List++;
242 const MCPhysReg (*RURoots)[2]
    [all...]
  /external/llvm/lib/Target/ARM/
ARMBaseRegisterInfo.h 76 const MCPhysReg *CSRegs) {
103 const MCPhysReg *
133 ArrayRef<MCPhysReg> Order,
134 SmallVectorImpl<MCPhysReg> &Hints,
ARMCallingConv.h 31 static const MCPhysReg RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
74 static const MCPhysReg HiRegList[] = { ARM::R0, ARM::R2 };
75 static const MCPhysReg LoRegList[] = { ARM::R1, ARM::R3 };
76 static const MCPhysReg ShadowRegList[] = { ARM::R0, ARM::R1 };
77 static const MCPhysReg GPRArgRegs[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
126 static const MCPhysReg HiRegList[] = { ARM::R0, ARM::R2 };
127 static const MCPhysReg LoRegList[] = { ARM::R1, ARM::R3 };
  /external/llvm/lib/Target/Hexagon/
HexagonRegisterInfo.h 51 const MCPhysReg *
  /external/llvm/lib/Target/NVPTX/
NVPTXRegisterInfo.h 44 const MCPhysReg *
NVPTXRegisterInfo.cpp 81 const MCPhysReg *
83 static const MCPhysReg CalleeSavedRegs[] = { 0 };
  /external/llvm/lib/Target/Sparc/
SparcRegisterInfo.h 34 const MCPhysReg *
  /external/llvm/lib/Target/SystemZ/
SystemZRegisterInfo.h 46 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF = nullptr) const
  /external/llvm/include/llvm/Target/
TargetRegisterInfo.h 38 typedef const MCPhysReg* iterator;
39 typedef const MCPhysReg* const_iterator;
49 ArrayRef<MCPhysReg> (*OrderFunc)(const MachineFunction&);
194 ArrayRef<MCPhysReg> getRawAllocationOrder(const MachineFunction &MF) const {
423 virtual const MCPhysReg*
651 ArrayRef<MCPhysReg> Order,
652 SmallVectorImpl<MCPhysReg> &Hints,
    [all...]
  /external/llvm/lib/Target/Mips/
MipsFrameLowering.cpp 113 for (const MCPhysReg *R = TRI.getCalleeSavedRegs(&MF); *R; ++R) {
MipsRegisterInfo.h 50 const MCPhysReg *
MipsRegisterInfo.cpp 82 const MCPhysReg *
128 static const MCPhysReg ReservedGPR32[] = {
132 static const MCPhysReg ReservedGPR64[] = {
  /external/llvm/lib/Target/X86/
X86RegisterInfo.h 99 const MCPhysReg *
  /external/llvm/lib/Target/AArch64/
AArch64RegisterInfo.h 39 const MCPhysReg *
  /external/llvm/lib/Target/PowerPC/
PPCRegisterInfo.h 47 const MCPhysReg *

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