| /external/llvm/lib/Target/ARM/ |
| Thumb2InstrInfo.cpp | 488 unsigned NewOpc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12;
489 MI.setDesc(TII.get(NewOpc));
522 unsigned NewOpc = Opcode;
532 NewOpc = immediateOffsetOpcode(Opcode);
544 NewOpc = negativeOffsetOpcode(Opcode);
549 NewOpc = positiveOffsetOpcode(Opcode);
579 if (NewOpc != Opcode)
580 MI.setDesc(TII.get(NewOpc));
613 MI.setDesc(TII.get(positiveOffsetOpcode(NewOpc)));
|
| ARMLoadStoreOptimizer.cpp | [all...] |
| ARMConstantIslandPass.cpp | [all...] |
| ARMExpandPseudoInsts.cpp | [all...] |
| ARMISelLowering.cpp | [all...] |
| Thumb1RegisterInfo.cpp | 460 unsigned NewOpc = convertToNonSPOpcode(Opcode);
461 if (NewOpc != Opcode && FrameReg != ARM::SP)
462 MI.setDesc(TII.get(NewOpc));
|
| /external/llvm/lib/Target/X86/ |
| X86MCInstLower.cpp | 421 unsigned NewOpc;
424 case X86::VMOVAPDrr: NewOpc = X86::VMOVAPDrr_REV; break;
425 case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV; break;
426 case X86::VMOVAPSrr: NewOpc = X86::VMOVAPSrr_REV; break;
427 case X86::VMOVAPSYrr: NewOpc = X86::VMOVAPSYrr_REV; break;
428 case X86::VMOVDQArr: NewOpc = X86::VMOVDQArr_REV; break;
429 case X86::VMOVDQAYrr: NewOpc = X86::VMOVDQAYrr_REV; break;
430 case X86::VMOVDQUrr: NewOpc = X86::VMOVDQUrr_REV; break;
431 case X86::VMOVDQUYrr: NewOpc = X86::VMOVDQUYrr_REV; break;
432 case X86::VMOVUPDrr: NewOpc = X86::VMOVUPDrr_REV; break
[all...] |
| X86InstrInfo.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64InstrInfo.cpp | 709 unsigned NewOpc;
713 case AArch64::ADDSWrr: NewOpc = AArch64::ADDWrr; break;
714 case AArch64::ADDSWri: NewOpc = AArch64::ADDWri; break;
715 case AArch64::ADDSWrs: NewOpc = AArch64::ADDWrs; break;
716 case AArch64::ADDSWrx: NewOpc = AArch64::ADDWrx; break;
717 case AArch64::ADDSXrr: NewOpc = AArch64::ADDXrr; break;
718 case AArch64::ADDSXri: NewOpc = AArch64::ADDXri; break;
719 case AArch64::ADDSXrs: NewOpc = AArch64::ADDXrs; break;
720 case AArch64::ADDSXrx: NewOpc = AArch64::ADDXrx; break;
721 case AArch64::SUBSWrr: NewOpc = AArch64::SUBWrr; break
[all...] |
| AArch64AdvSIMDScalarPass.cpp | 283 int NewOpc = getTransformOpcode(OldOpc);
284 assert(OldOpc != NewOpc && "transform an instruction to itself?!");
338 BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(NewOpc), Dst)
|
| AArch64LoadStoreOptimizer.cpp | 286 unsigned NewOpc = getMatchingPairOpcode(I->getOpcode());
312 I->getDebugLoc(), TII->get(NewOpc))
538 unsigned NewOpc = getPreIndexedOpcode(I->getOpcode());
540 BuildMI(*I->getParent(), I, I->getDebugLoc(), TII->get(NewOpc))
581 unsigned NewOpc = getPostIndexedOpcode(I->getOpcode());
583 BuildMI(*I->getParent(), I, I->getDebugLoc(), TII->get(NewOpc))
[all...] |
| AArch64ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEInstrInfo.h | 90 unsigned NewOpc) const;
|
| MipsInstrInfo.h | 122 MachineInstrBuilder genInstrWithNewOpc(unsigned NewOpc,
|
| MipsSEISelLowering.h | 66 SDValue lowerMulDiv(SDValue Op, unsigned NewOpc, bool HasLo, bool HasHi,
|
| MipsInstrInfo.cpp | 285 MipsInstrInfo::genInstrWithNewOpc(unsigned NewOpc,
288 MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), get(NewOpc));
|
| MipsLongBranch.cpp | 221 unsigned NewOpc = TII->getOppositeBranchOpc(Br->getOpcode());
222 const MCInstrDesc &NewDesc = TII->get(NewOpc);
|
| MipsSEInstrInfo.cpp | 455 unsigned NewOpc) const {
456 BuildMI(MBB, I, I->getDebugLoc(), get(NewOpc), I->getOperand(0).getReg());
|
| /external/llvm/lib/Target/X86/AsmParser/ |
| X86AsmParser.cpp | [all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| AMDILISelDAGToDAG.cpp | 166 unsigned int NewOpc = AMDGPU::COPY;
168 return CurDAG->SelectNodeTo(N, NewOpc, OpVT, TFI);
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDILISelDAGToDAG.cpp | 166 unsigned int NewOpc = AMDGPU::COPY;
168 return CurDAG->SelectNodeTo(N, NewOpc, OpVT, TFI);
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorOps.cpp | 420 unsigned NewOpc;
425 NewOpc = ISD::FP_TO_SINT;
429 NewOpc = ISD::FP_TO_UINT;
435 SDValue promoted = DAG.getNode(NewOpc, SDLoc(Op), NewVT, Op.getOperand(0));
[all...] |
| /external/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | [all...] |
| /external/llvm/lib/CodeGen/ |
| MachineLICM.cpp | [all...] |
| /external/llvm/lib/Target/R600/ |
| SIInstrInfo.cpp | 172 int NewOpc;
175 if ((NewOpc = AMDGPU::getCommuteRev(Opcode)) != -1)
176 return NewOpc;
179 if ((NewOpc = AMDGPU::getCommuteOrig(Opcode)) != -1)
180 return NewOpc;
[all...] |
