| /external/llvm/lib/Target/ARM/ |
| Thumb2RegisterInfo.h | 33 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0,
|
| ARMLoadStoreOptimizer.cpp | 103 ARMCC::CondCodes Pred, unsigned PredReg);
106 ARMCC::CondCodes Pred, unsigned PredReg, unsigned Scratch,
120 unsigned PredReg,
126 ARMCC::CondCodes Pred, unsigned PredReg,
336 ARMCC::CondCodes Pred, unsigned PredReg) {
388 .addImm(Pred).addReg(PredReg);
406 .addImm(Pred).addReg(PredReg);
417 unsigned PredReg, unsigned Scratch, DebugLoc dl,
481 .addImm(Pred).addReg(PredReg);
485 .addImm(Pred).addReg(PredReg);
[all...] |
| Thumb1RegisterInfo.h | 41 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0,
|
| Thumb2RegisterInfo.cpp | 40 ARMCC::CondCodes Pred, unsigned PredReg,
|
| Thumb2InstrInfo.cpp | 61 unsigned PredReg = 0;
62 ARMCC::CondCodes CC = getInstrPredicate(Tail, PredReg);
109 unsigned PredReg = 0;
110 return getITInstrPredicate(MBBI, PredReg) == ARMCC::AL;
215 ARMCC::CondCodes Pred, unsigned PredReg,
220 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
237 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
244 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
253 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
259 .addImm((unsigned)Pred).addReg(PredReg).addReg(0
[all...] |
| Thumb2InstrInfo.h | 69 ARMCC::CondCodes getITInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
|
| Thumb2ITBlockPass.cpp | 171 unsigned PredReg = 0;
172 ARMCC::CondCodes CC = getITInstrPredicate(MI, PredReg);
|
| ARMBaseRegisterInfo.cpp | 403 unsigned PredReg, unsigned MIFlags) const {
414 .addImm(0).addImm(Pred).addReg(PredReg)
760 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
768 Offset, Pred, PredReg, TII);
772 Offset, Pred, PredReg, TII);
|
| ARMBaseInstrInfo.h | 382 ARMCC::CondCodes getInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
403 ARMCC::CondCodes Pred, unsigned PredReg,
409 ARMCC::CondCodes Pred, unsigned PredReg,
|
| MLxExpansionPass.cpp | 285 unsigned PredReg = MI->getOperand(++NextOp).getReg();
298 MIB.addImm(Pred).addReg(PredReg);
310 MIB.addImm(Pred).addReg(PredReg);
|
| ARMBaseRegisterInfo.h | 173 unsigned PredReg = 0,
|
| Thumb2SizeReduction.cpp | 581 unsigned PredReg = 0;
582 if (getInstrPredicate(MI, PredReg) == ARMCC::AL) {
685 unsigned PredReg = 0;
686 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
782 unsigned PredReg = 0;
783 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
[all...] |
| Thumb1RegisterInfo.cpp | 67 ARMCC::CondCodes Pred, unsigned PredReg,
78 .addConstantPoolIndex(Idx).addImm(Pred).addReg(PredReg)
371 unsigned PredReg;
372 if (Offset == 0 && getInstrPredicate(&MI, PredReg) == ARMCC::AL) {
|
| ARMFrameLowering.cpp | 120 unsigned PredReg = 0) {
123 Pred, PredReg, TII, MIFlags);
126 Pred, PredReg, TII, MIFlags);
134 unsigned PredReg = 0) {
136 MIFlags, Pred, PredReg);
[all...] |
| ARMConstantIslandPass.cpp | [all...] |
| ARMExpandPseudoInsts.cpp | [all...] |
| ARMBaseInstrInfo.cpp | [all...] |
| ARMISelDAGToDAG.cpp | [all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonHardwareLoops.cpp | 500 unsigned PredReg = Cond[Cond.size()-1].getReg();
501 MachineInstr *CondI = MRI->getVRegDef(PredReg);
[all...] |
