/external/llvm/lib/Target/Mips/ |
MipsAnalyzeImmediate.cpp | 45 AddInstr(SeqLs, Inst(SLL, Shamt)); 79 // Replace a ADDiu & SLL pair with a LUi. 82 // SLL 18 86 // Check if the first two instructions are ADDiu and SLL and the shift amount 89 (Seq[1].Opc != SLL) || (Seq[1].ImmOpnd < 16)) 132 SLL = Mips::SLL; 137 SLL = Mips::DSLL;
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MipsAnalyzeImmediate.h | 43 /// GetInstSeqLsSLL - Get instruction sequences which end with a SLL to 50 /// ReplaceADDiuSLLWithLUi - Replace an ADDiu & SLL pair with a LUi. 58 unsigned ADDiu, ORi, SLL, LUi;
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MipsCodeEmitter.cpp | 380 BuildMI(MBB, &*MI, MI->getDebugLoc(), II->get(Mips::SLL), Mips::ZERO)
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MipsISelLowering.cpp | [all...] |
MipsSEISelLowering.cpp | [all...] |
/external/openssl/crypto/bn/asm/ |
mips.pl | 63 $SLL="dsll"; 78 $SLL="sll"; 890 $SLL $a2,1 897 $SLL $t2,$t1 905 $SLL $a0,$t9 906 $SLL $a1,$t9 930 $SLL $t3,$a0,4*$BNSZ # bits 951 $SLL $a1,4*$BNSZ # bits 953 $SLL $v0,$QT,4*$BNSZ # bit [all...] |
/external/openssl/crypto/sha/asm/ |
sha512-mips.pl | 62 $PTR_SLL="sll"; 83 $SLL="dsll"; # shift left logical 97 $SLL="sll"; # shift left logical 130 sll @X[0],@X[0],24 132 sll $tmp2,$tmp2,8 161 $SLL $tmp1,$e,`$SZ*8-@Sigma1[2]` 165 $SLL $tmp1,$e,`$SZ*8-@Sigma1[1]` 169 $SLL $tmp1,$e,`$SZ*8-@Sigma1[0]` 177 $SLL $tmp1,$a,`$SZ*8-@Sigma0[2] [all...] |
sha512-sparcv9.pl | 58 $SLL="sllx"; # shift left logical 84 $SLL="sll"; # shift left logical 224 $SLL $e,`$SZ*8-@Sigma1[2]`,$tmp1 228 $SLL $e,`$SZ*8-@Sigma1[1]`,$tmp1 232 $SLL $e,`$SZ*8-@Sigma1[0]`,$tmp1 240 $SLL $a,`$SZ*8-@Sigma0[2]`,$tmp1 244 $SLL $a,`$SZ*8-@Sigma0[1]`,$tmp1 248 $SLL $a,`$SZ*8-@Sigma0[0]`,$tmp1 277 sll $xi,`32-@sigma0[2]`,$tmp [all...] |
/external/clang/test/CodeGen/ |
xcore-stringtype.c | 21 // CHECK: ul,sl,sll,ull,sll,ft,d,ld)"} 25 long long LL, unsigned long long ULL, signed long long SLL,
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/external/chromium_org/v8/src/mips/ |
constants-mips.cc | 224 case SLL:
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constants-mips.h | 372 SLL = ((0 << 3) + 0), 726 // A nop instruction. (Encoding of sll 0 0 0).
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macro-assembler-mips.h | 455 // i.e. check if it is a sll zero_reg, zero_reg, <type> (referenced as 470 // Return <n> if we have a sll zero_reg, zero_reg, n 472 bool sllzz = (opcode == SLL && [all...] |
assembler-mips.cc | 595 // Traditional mips nop == sll(zero_reg, zero_reg, 0) 596 // When marking non-zero type, use sll(zero_reg, at, type) 598 // of the sll instruction. 601 bool ret = (opcode == SPECIAL && function == SLL && 1597 void Assembler::sll(Register rd, function in class:v8::Assembler [all...] |
simulator-mips.cc | [all...] |
/external/chromium_org/v8/src/mips64/ |
constants-mips64.cc | 224 case SLL:
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constants-mips64.h | 349 SLL = ((0 << 3) + 0), 740 // A nop instruction. (Encoding of sll 0 0 0).
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macro-assembler-mips64.h | 476 // i.e. check if it is a sll zero_reg, zero_reg, <type> (referenced as 491 // Return <n> if we have a sll zero_reg, zero_reg, n 493 bool sllzz = (opcode == SLL && [all...] |
assembler-mips64.cc | 567 // Traditional mips nop == sll(zero_reg, zero_reg, 0) 568 // When marking non-zero type, use sll(zero_reg, at, type) 570 // of the sll instruction. 573 bool ret = (opcode == SPECIAL && function == SLL && 1661 void Assembler::sll(Register rd, function in class:v8::Assembler [all...] |
simulator-mips64.cc | [all...] |
/external/linux-tools-perf/perf-3.12.0/arch/mips/lib/ |
memcpy.S | 113 #define SLL dsll 148 #define SLL sll 328 SLL rem, len, 3 # rem = number of bits to keep
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/external/llvm/lib/Target/Mips/MCTargetDesc/ |
MipsMCCodeEmitter.cpp | 173 // Unfortunately in MIPS both NOP and SLL will come in with Binary == 0 176 if ((Opcode != Mips::NOP) && (Opcode != Mips::SLL) && !Binary)
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/external/clang/lib/Sema/ |
SemaOverload.cpp | [all...] |
/external/oprofile/events/mips/74K/ |
events | 60 event:0x2b counters:0,2 um:zero minimum:500 name:NOP_INSNS : 43-0 NOP instructions graduated - SLL 0, NOP, SSNOP, and EHB
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/external/llvm/lib/Target/Mips/AsmParser/ |
MipsAsmParser.cpp | [all...] |
/external/chromium_org/chrome/third_party/chromevox/ |
chromeVoxChromeBackgroundScript.js | [all...] |