| /art/compiler/dex/quick/arm/ |
| int_arm.cc | 43 LIR* ArmMir2Lir::OpIT(ConditionCode ccode, const char* guide) {
48 ArmConditionCode code = ArmConditionEncoding(ccode);
156 int64_t val, ConditionCode ccode) {
167 if (val == 0 && (ccode == kCondEq || ccode == kCondNe)) {
171 OpCondBranch(ccode, taken);
175 switch (ccode) {
178 OpCmpImmBranch(kCondNe, high_reg, val_hi, (ccode == kCondEq) ? not_taken : taken);
183 ccode = kCondUlt;
188 ccode = kCondLs
238 ConditionCode ccode = mir->meta.ccode; local
309 ConditionCode ccode = mir->meta.ccode; local
[all...] |
| fp_arm.cc | 233 ConditionCode ccode = mir->meta.ccode; local
234 switch (ccode) {
240 ccode = kCondMi;
245 ccode = kCondLs;
250 ccode = kCondHi;
255 ccode = kCondUge;
259 LOG(FATAL) << "Unexpected ccode: " << ccode;
261 OpCondBranch(ccode, target)
[all...] |
| target_arm.cc | 242 ArmConditionCode ArmMir2Lir::ArmConditionEncoding(ConditionCode ccode) {
244 switch (ccode) {
264 LOG(FATAL) << "Bad condition code " << ccode;
|
| codegen_arm.h | 195 ConditionCode ccode);
|
| /art/compiler/dex/quick/arm64/ |
| fp_arm64.cc | 219 ConditionCode ccode = mir->meta.ccode; local
220 switch (ccode) {
226 ccode = kCondMi;
231 ccode = kCondLs;
236 ccode = kCondHi;
241 ccode = kCondUge;
245 LOG(FATAL) << "Unexpected ccode: " << ccode;
247 OpCondBranch(ccode, target)
[all...] |
| int_arm64.cc | 34 LIR* Arm64Mir2Lir::OpIT(ConditionCode ccode, const char* guide) {
91 void Arm64Mir2Lir::GenSelect(int32_t true_val, int32_t false_val, ConditionCode ccode,
97 ccode = NegateComparison(ccode);
101 ArmConditionCode code = ArmConditionEncoding(ccode);
194 GenSelect(mir->dalvikInsn.vB, mir->dalvikInsn.vC, mir->meta.ccode, rl_result.reg,
209 rl_true.reg.GetReg(), rl_false.reg.GetReg(), ArmConditionEncoding(mir->meta.ccode));
220 ConditionCode ccode = mir->meta.ccode; local
223 ccode = FlipComparisonOrder(ccode)
[all...] |
| target_arm64.cc | 188 ArmConditionCode Arm64Mir2Lir::ArmConditionEncoding(ConditionCode ccode) {
190 switch (ccode) {
210 LOG(FATAL) << "Bad condition code " << ccode;
[all...] |
| /art/compiler/dex/quick/x86/ |
| fp_x86.cc | 513 ConditionCode ccode = mir->meta.ccode; local
514 switch (ccode) {
532 ccode = kCondUlt;
539 ccode = kCondLs;
546 ccode = kCondHi;
553 ccode = kCondUge;
556 LOG(FATAL) << "Unexpected ccode: " << ccode;
558 OpCondBranch(ccode, taken)
[all...] |
| int_x86.cc | 277 ConditionCode ccode = mir->meta.ccode; local
296 * For ccode == kCondEq:
335 ConditionCode cc = true_zero_case ? NegateComparison(ccode) : ccode;
354 * For ccode == kCondEq:
372 OpCondRegReg(kOpCmov, NegateComparison(ccode), rl_result.reg, rl_false.reg);
374 OpCondRegReg(kOpCmov, ccode, rl_result.reg, rl_true.reg);
377 OpCondRegReg(kOpCmov, ccode, rl_result.reg, rl_true.reg);
388 ConditionCode ccode = mir->meta.ccode local
[all...] |
| codegen_x86.h | 480 int64_t val, ConditionCode ccode);
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/nv50/codegen/ |
| nv50_ir.cpp | 816 Instruction::setPredicate(CondCode ccode, Value *value)
818 cc = ccode;
|
| nv50_ir.h | 629 bool setPredicate(CondCode ccode, Value *);
|
| /external/mesa3d/src/gallium/drivers/nv50/codegen/ |
| nv50_ir.cpp | 816 Instruction::setPredicate(CondCode ccode, Value *value)
818 cc = ccode;
|
| nv50_ir.h | 629 bool setPredicate(CondCode ccode, Value *);
|
| /art/compiler/dex/ |
| mir_optimization.cc | 359 mir_next->meta.ccode = ConditionCodeForIfCcZ(mir_next->dalvikInsn.opcode);
481 mir->meta.ccode = ConditionCodeForIfCcZ(mir->dalvikInsn.opcode);
[all...] |
| mir_graph.h | 360 ConditionCode ccode; member in union:art::MIR::__anon7
[all...] |
