/external/fio/engines/ |
rdma.c | 121 struct rdmaio_data *rd = td->io_ops->data; local 123 if (wc->byte_len != sizeof(rd->recv_buf)) { 129 if ((rd->rdma_protocol == FIO_RDMA_MEM_WRITE) || 130 (rd->rdma_protocol == FIO_RDMA_MEM_READ)) { 134 rd->rmt_nr = ntohl(rd->recv_buf.nr); 136 for (i = 0; i < rd->rmt_nr; i++) { 137 rd->rmt_us[i].buf = ntohll(rd->recv_buf.rmt_us[i].buf); 138 rd->rmt_us[i].rkey = ntohl(rd->recv_buf.rmt_us[i].rkey) 153 struct rdmaio_data *rd = td->io_ops->data; local 168 struct rdmaio_data *rd = td->io_ops->data; local 275 struct rdmaio_data *rd = td->io_ops->data; local 312 struct rdmaio_data *rd = td->io_ops->data; local 392 struct rdmaio_data *rd = td->io_ops->data; local 436 struct rdmaio_data *rd = td->io_ops->data; local 468 struct rdmaio_data *rd = td->io_ops->data; local 511 struct rdmaio_data *rd = td->io_ops->data; local 529 struct rdmaio_data *rd = td->io_ops->data; local 591 struct rdmaio_data *rd = td->io_ops->data; local 654 struct rdmaio_data *rd = td->io_ops->data; local 690 struct rdmaio_data *rd = td->io_ops->data; local 708 struct rdmaio_data *rd = td->io_ops->data; local 731 struct rdmaio_data *rd = td->io_ops->data; local 763 struct rdmaio_data *rd = td->io_ops->data; local 812 struct rdmaio_data *rd = td->io_ops->data; local 855 struct rdmaio_data *rd = td->io_ops->data; local 911 struct rdmaio_data *rd = td->io_ops->data; local 975 struct rdmaio_data *rd = td->io_ops->data; local 1051 struct rdmaio_data *rd = td->io_ops->data; local 1191 struct rdmaio_data *rd = td->io_ops->data; local 1199 struct rdmaio_data *rd; local [all...] |
/external/clang/test/CXX/temp/temp.param/ |
p7.cpp | 9 template<double& rd> class Z; //OK
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/external/chromium_org/v8/src/arm64/ |
macro-assembler-arm64-inl.h | 46 void MacroAssembler::And(const Register& rd, 50 DCHECK(!rd.IsZero()); 51 LogicalMacro(rd, rn, operand, AND); 55 void MacroAssembler::Ands(const Register& rd, 59 DCHECK(!rd.IsZero()); 60 LogicalMacro(rd, rn, operand, ANDS); 71 void MacroAssembler::Bic(const Register& rd, 75 DCHECK(!rd.IsZero()); 76 LogicalMacro(rd, rn, operand, BIC); 80 void MacroAssembler::Bics(const Register& rd, [all...] |
assembler-arm64.h | [all...] |
delayed-masm-arm64-inl.h | 23 void DelayedMasm::Mov(const Register& rd, 27 DCHECK(!IsScratchRegister(rd) || scratch_register_acquired_); 28 __ Mov(rd, operand, discard_mode);
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assembler-arm64.cc | 522 // Instruction to patch must be 'ldr rd, [pc, #offset]' with offset == 0. 538 // Instruction to patch must be 'ldr rd, [pc, #offset]' with offset == 0. 3128 Register rd = Register::XRegFromCode(rd_code); local [all...] |
macro-assembler-arm64.h | 140 inline void And(const Register& rd, 143 inline void Ands(const Register& rd, 146 inline void Bic(const Register& rd, 149 inline void Bics(const Register& rd, 152 inline void Orr(const Register& rd, 155 inline void Orn(const Register& rd, 158 inline void Eor(const Register& rd, 161 inline void Eon(const Register& rd, 165 void LogicalMacro(const Register& rd, 171 inline void Add(const Register& rd, [all...] |
delayed-masm-arm64.cc | 100 void DelayedMasm::Load(const CPURegister& rd, const MemOperand& operand) { 102 pending_register_.IsSameSizeAndType(rd)) { 110 DCHECK(!IsScratchRegister(rd) || scratch_register_acquired_); 111 __ Ldp(pending_register_, rd, pending_address_src_); 118 DCHECK(!IsScratchRegister(rd) || scratch_register_acquired_); 119 __ Ldp(rd, pending_register_, operand); 127 pending_register_ = rd; 135 void DelayedMasm::Store(const CPURegister& rd, const MemOperand& operand) { 137 pending_register_.IsSameSizeAndType(rd)) { 143 __ Stp(pending_register_, rd, pending_address_dst_) [all...] |
/external/chromium_org/third_party/icu/source/test/cintltst/ |
uregiontest.c | 362 const KnownRegion * rd; local 363 for (rd = knownRegions; rd->code != NULL ; rd++ ) { 365 const URegion *r = uregion_getRegionFromCode(rd->code, &status); 368 int32_t e = rd->numeric; 372 if (uregion_getType(r) != rd->type) { 373 log_err("ERROR: Expected region %s to be of type %d. Got: %d\n", uregion_getRegionCode(r), rd->type, uregion_getType(r) ); 383 log_data_err("ERROR: Known region %s was not recognized.\n", rd->code); 389 const KnownRegion * rd; local 418 const KnownRegion * rd; local 447 const KnownRegion * rd; local 471 const KnownRegion * rd; local 548 const KnownRegion * rd; local [all...] |
/external/icu/icu4c/source/test/cintltst/ |
uregiontest.c | 362 const KnownRegion * rd; local 363 for (rd = knownRegions; rd->code != NULL ; rd++ ) { 365 const URegion *r = uregion_getRegionFromCode(rd->code, &status); 368 int32_t e = rd->numeric; 372 if (uregion_getType(r) != rd->type) { 373 log_err("ERROR: Expected region %s to be of type %d. Got: %d\n", uregion_getRegionCode(r), rd->type, uregion_getType(r) ); 383 log_data_err("ERROR: Known region %s was not recognized.\n", rd->code); 389 const KnownRegion * rd; local 418 const KnownRegion * rd; local 447 const KnownRegion * rd; local 471 const KnownRegion * rd; local 548 const KnownRegion * rd; local [all...] |
/external/chromium_org/third_party/libvpx/source/libvpx/vp9/encoder/ |
vp9_rd.c | 47 // The baseline rd thresholds for breaking out of the rd loop for 219 static void set_block_thresholds(const VP9_COMMON *cm, RD_OPT *rd) { 236 rd->threshes[segment_id][bsize][i] = 237 rd->thresh_mult[i] < thresh_max 238 ? rd->thresh_mult[i] * t / 4 242 rd->threshes[segment_id][bsize][i] = 243 rd->thresh_mult_sub8x8[i] < thresh_max 244 ? rd->thresh_mult_sub8x8[i] * t / 4 254 RD_OPT *const rd = &cpi->rd local 525 RD_OPT *const rd = &cpi->rd; local 583 RD_OPT *const rd = &cpi->rd; local [all...] |
/external/llvm/lib/Target/Sparc/ |
SparcJITInfo.cpp | 102 #define SETHI_INST(imm, rd) (0x01000000 | ((rd) << 25) | ((imm) & 0x3FFFFF)) 103 #define JMP_INST(rs1, imm, rd) (0x80000000 | ((rd) << 25) | (0x38 << 19) \ 106 #define OR_INST_I(rs1, imm, rd) (0x80000000 | ((rd) << 25) | (0x02 << 19) \ 108 #define OR_INST_R(rs1, rs2, rd) (0x80000000 | ((rd) << 25) | (0x02 << 19) \ 110 #define RDPC_INST(rd) (0x80000000 | ((rd) << 25) | (0x28 << 19) [all...] |
/art/compiler/utils/arm/ |
assembler_thumb2.h | 65 void and_(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE; 67 void eor(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE; 69 void sub(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE; 70 void subs(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE; 72 void rsb(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE; 73 void rsbs(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE; 75 void add(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE; 77 void adds(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE; 79 void adc(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE; 81 void sbc(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE [all...] |
assembler_arm32.h | 43 void and_(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE; 45 void eor(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE; 47 void sub(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE; 48 void subs(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE; 50 void rsb(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE; 51 void rsbs(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE; 53 void add(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE; 55 void adds(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE; 57 void adc(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE; 59 void sbc(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE [all...] |
assembler_arm32.cc | 28 void Arm32Assembler::and_(Register rd, Register rn, const ShifterOperand& so, 30 EmitType01(cond, so.type(), AND, 0, rn, rd, so); 34 void Arm32Assembler::eor(Register rd, Register rn, const ShifterOperand& so, 36 EmitType01(cond, so.type(), EOR, 0, rn, rd, so); 40 void Arm32Assembler::sub(Register rd, Register rn, const ShifterOperand& so, 42 EmitType01(cond, so.type(), SUB, 0, rn, rd, so); 45 void Arm32Assembler::rsb(Register rd, Register rn, const ShifterOperand& so, 47 EmitType01(cond, so.type(), RSB, 0, rn, rd, so); 50 void Arm32Assembler::rsbs(Register rd, Register rn, const ShifterOperand& so, 52 EmitType01(cond, so.type(), RSB, 1, rn, rd, so) [all...] |
assembler_arm.h | 128 static bool CanHoldThumb(Register rd, Register rn, Opcode opcode, 363 virtual void and_(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) = 0; 365 virtual void eor(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) = 0; 367 virtual void sub(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) = 0; 368 virtual void subs(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) = 0; 370 virtual void rsb(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) = 0; 371 virtual void rsbs(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) = 0; 373 virtual void add(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) = 0; 375 virtual void adds(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) = 0; 377 virtual void adc(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) = 0 [all...] |
assembler_thumb2.cc | 28 void Thumb2Assembler::and_(Register rd, Register rn, const ShifterOperand& so, 30 EmitDataProcessing(cond, AND, 0, rn, rd, so); 34 void Thumb2Assembler::eor(Register rd, Register rn, const ShifterOperand& so, 36 EmitDataProcessing(cond, EOR, 0, rn, rd, so); 40 void Thumb2Assembler::sub(Register rd, Register rn, const ShifterOperand& so, 42 EmitDataProcessing(cond, SUB, 0, rn, rd, so); 46 void Thumb2Assembler::rsb(Register rd, Register rn, const ShifterOperand& so, 48 EmitDataProcessing(cond, RSB, 0, rn, rd, so); 52 void Thumb2Assembler::rsbs(Register rd, Register rn, const ShifterOperand& so, 54 EmitDataProcessing(cond, RSB, 1, rn, rd, so) [all...] |
/external/clang/test/CXX/dcl.decl/dcl.init/dcl.init.ref/ |
p5-examples.cpp | 6 // CHECK: VarDecl{{.*}}rd 'double &' 8 double &rd = d; local
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/external/chromium_org/third_party/libwebp/enc/ |
quant.c | 54 const VP8ModeScore* const rd) { 70 (int)rd->D, (int)rd->SD, (int)rd->R, (int)rd->H, (int)rd->nz, 71 (int)rd->score); 73 printf("Mode: %d\n", rd->mode_i16); 75 for (i = 0; i < 16; ++i) printf("%3d ", rd->y_dc_levels[i]); 79 for (i = 0; i < 16; ++i) printf("%d ", rd->modes_i4[i]) [all...] |
/external/openssl/crypto/bn/asm/ |
sparcv8.S | 63 rd %y,%g1 74 rd %y,%g1 85 rd %y,%g1 95 rd %y,%g1 117 rd %y,%g1 128 rd %y,%g1 140 rd %y,%g1 176 rd %y,%g1 183 rd %y,%g1 191 rd %y,%g [all...] |
/external/chromium_org/v8/src/mips64/ |
disasm-mips64.cc | 193 // Print the integer value of the rd field, when it is not used as reg. 200 // Print the integer value of the rd field, when used as 'ext' size. 207 // Print the integer value of the rd field, when used as 'ins' size. 310 } else if (format[1] == 'd') { // 'rd: rd register. 670 Format(instr, "sll 'rd, 'rt, 'sa"); 673 Format(instr, "dsll 'rd, 'rt, 'sa"); 680 Format(instr, "dmul 'rd, 'rs, 'rt"); 682 Format(instr, "dmuh 'rd, 'rs, 'rt"); 687 Format(instr, "dsll32 'rd, 'rt, 'sa") [all...] |
assembler-mips64.h | 77 static const int kCpRegister = 23; // cp (s7) is the 23rd register. 733 void jalr(Register rs, Register rd = ra); 742 void addu(Register rd, Register rs, Register rt); 743 void subu(Register rd, Register rs, Register rt); 749 void div(Register rd, Register rs, Register rt); 750 void divu(Register rd, Register rs, Register rt); 751 void ddiv(Register rd, Register rs, Register rt); 752 void ddivu(Register rd, Register rs, Register rt); 753 void mod(Register rd, Register rs, Register rt); 754 void modu(Register rd, Register rs, Register rt) [all...] |
assembler-mips64.cc | 350 Register rd; local 351 rd.code_ = (instr & kRdFieldMask) >> kRdShift; 352 return rd; 564 uint32_t rd = GetRd(instr); 574 rd == static_cast<uint32_t>(ToNumber(zero_reg)) && 853 Register rd, 856 DCHECK(rd.is_valid() && rs.is_valid() && rt.is_valid() && is_uint5(sa)); 858 | (rd.code() << kRdShift) | (sa << kSaShift) | func; [all...] |
/development/ndk/platforms/android-9/arch-mips/include/asm/ |
asm.h | 60 #define MOVN(rd, rs, rt) .set push; .set reorder; beqz rt, 9f; move rd, rs; .set pop; 9: 61 #define MOVZ(rd, rs, rt) .set push; .set reorder; bnez rt, 9f; move rd, rs; .set pop; 9: 65 #define MOVN(rd, rs, rt) .set push; .set noreorder; bnezl rt, 9f; move rd, rs; .set pop; 9: 66 #define MOVZ(rd, rs, rt) .set push; .set noreorder; beqzl rt, 9f; move rd, rs; .set pop; 9: 70 #define MOVN(rd, rs, rt) movn rd, rs, r [all...] |
/external/chromium_org/v8/src/arm/ |
disasm-arm.cc | 307 } else if (format[1] == 'd') { // 'rd: Rd register 437 int rd = instr->RdValue(); local 438 PrintRegister(rd); 710 // The MUL instruction description (A 4.1.33) refers to Rd as being 717 // of registers as "Rd, Rm, Rs, Rn". But confusingly it uses the 718 // Rn field to encode the Rd register and the Rd field to encode 720 Format(instr, "mla'cond's 'rn, 'rm, 'rs, 'rd"); 723 // of registers as "Rd, Rm, Rs, Rn". But confusingly it uses th [all...] |