| /external/llvm/test/MC/Mips/ |
| micromips-loadstore-unaligned.s | 15 # CHECK-EL: swr $4, 16($5) # encoding: [0x85,0x60,0x10,0x90]
22 # CHECK-EB: swr $4, 16($5) # encoding: [0x60,0x85,0x90,0x10]
26 swr $4, 16($5)
|
| nacl-mask.s | 120 swr $4, 0($7)
153 # CHECK-NEXT: swr $4, 0($7)
|
| /external/llvm/test/MC/Mips/mips32r6/ |
| invalid-mips1-wrong-error.s | 13 swr $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
| /external/llvm/test/MC/Mips/mips64r6/ |
| invalid-mips1-wrong-error.s | 13 swr $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
| invalid-mips3-wrong-error.s | 19 swr $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
| /bionic/libc/arch-mips/include/machine/ |
| asm.h | 68 #define SWHI swr
77 #define SWLO swr
|
| /bionic/libc/arch-mips64/include/machine/ |
| asm.h | 68 #define SWHI swr
77 #define SWLO swr
|
| /development/ndk/platforms/android-L/arch-mips/include/machine/ |
| asm.h | 68 #define SWHI swr
77 #define SWLO swr
|
| /development/ndk/platforms/android-L/arch-mips64/include/machine/ |
| asm.h | 68 #define SWHI swr
77 #define SWLO swr
|
| /bionic/libc/arch-mips/string/ |
| memset.S | 51 # define SWLO swr /* low part is right in big-endian */
55 # define SWHI swr /* high part is right in little-endian */
|
| memcpy.S | 53 # define SWLO swr /* low part is right in big-endian */
58 # define SWHI swr /* high part is right in little-endian */
|
| /bionic/libc/arch-mips64/string/ |
| memset.S | 51 # define SWLO swr /* low part is right in big-endian */
55 # define SWHI swr /* high part is right in little-endian */
|
| memcpy.S | 53 # define SWLO swr /* low part is right in big-endian */
58 # define SWHI swr /* high part is right in little-endian */
|
| /development/ndk/platforms/android-9/arch-mips/include/machine/ |
| asm.h | 71 #define SWHI swr
80 #define SWLO swr
|
| /external/linux-tools-perf/perf-3.12.0/arch/mips/lib/ |
| memset.S | 17 #define LONG_S_R swr
|
| memcpy.S | 143 #define STORER swr
|
| /external/llvm/test/MC/Mips/mips1/ |
| valid.s | 108 swr $s1,-26590($14)
|
| /external/openssl/crypto/aes/asm/ |
| aes-mips.S | 288 swr $8,0+0($5)
289 swr $9,4+0($5)
290 swr $10,8+0($5)
291 swr $11,12+0($5)
595 swr $8,0+0($5)
596 swr $9,4+0($5)
597 swr $10,8+0($5)
598 swr $11,12+0($5)
|
| aes-mips.pl | 406 swr $s0,0+$LSB($out)
407 swr $s1,4+$LSB($out)
408 swr $s2,8+$LSB($out)
409 swr $s3,12+$LSB($out)
743 swr $s0,0+$LSB($out)
744 swr $s1,4+$LSB($out)
745 swr $s2,8+$LSB($out)
746 swr $s3,12+$LSB($out)
[all...] |
| /external/llvm/test/MC/Mips/mips2/ |
| valid.s | 124 swr $s1,-26590($14)
|
| /external/llvm/test/MC/Mips/mips32/ |
| valid.s | 151 swr $s1,-26590($14)
|
| /external/llvm/test/MC/Mips/mips32r2/ |
| valid.s | 180 swr $s1,-26590($14)
|
| /external/chromium_org/v8/src/mips/ |
| disasm-mips.cc | [all...] |
| /external/chromium_org/v8/test/cctest/ |
| test-assembler-mips.cc | 823 // Test LWL, LWR, SWL and SWR instructions.
907 // Test all combinations of SWR and vAddr.
911 __ swr(t0, MemOperand(a0, OFFSET_OF(T, swr_0)) );
916 __ swr(t1, MemOperand(a0, OFFSET_OF(T, swr_1) + 1) );
921 __ swr(t2, MemOperand(a0, OFFSET_OF(T, swr_2) + 2) );
926 __ swr(t3, MemOperand(a0, OFFSET_OF(T, swr_3) + 3) );
[all...] |
| test-assembler-mips64.cc | 857 // Test LWL, LWR, SWL and SWR instructions.
941 // Test all combinations of SWR and vAddr.
945 __ swr(a4, MemOperand(a0, OFFSET_OF(T, swr_0)));
950 __ swr(a5, MemOperand(a0, OFFSET_OF(T, swr_1) + 1));
955 __ swr(a6, MemOperand(a0, OFFSET_OF(T, swr_2) + 2));
960 __ swr(a7, MemOperand(a0, OFFSET_OF(T, swr_3) + 3));
[all...] |
