| /external/chromium_org/third_party/mesa/src/src/gallium/auxiliary/rbug/ |
| rbug_proto.h | 76 enum rbug_opcode opcode; member in struct:rbug_header
85 int32_t opcode; member in struct:rbug_proto_header
95 * Get printable string for opcode.
97 const char* rbug_proto_get_name(enum rbug_opcode opcode);
|
| /external/chromium_org/third_party/mesa/src/src/gallium/state_trackers/d3d1x/d3d1xshader/src/ |
| sm4_analyze.cpp | 45 switch(program.insns[insn_num]->opcode)
53 check(program.insns[v]->opcode == SM4_OPCODE_LOOP);
67 if(program.insns[insn_num]->opcode == SM4_OPCODE_ELSE)
68 check(program.insns[v]->opcode == SM4_OPCODE_IF);
70 check(program.insns[v]->opcode == SM4_OPCODE_SWITCH || program.insns[v]->opcode == SM4_OPCODE_CASE);
79 if(program.insns[insn_num]->opcode == SM4_OPCODE_ENDIF)
80 check(program.insns[v]->opcode == SM4_OPCODE_IF || program.insns[v]->opcode == SM4_OPCODE_ELSE);
82 check(program.insns[v]->opcode == SM4_OPCODE_SWITCH || program.insns[v]->opcode == SM4_OPCODE_CASE)
[all...] |
| /external/mesa3d/src/gallium/auxiliary/rbug/ |
| rbug_proto.h | 76 enum rbug_opcode opcode; member in struct:rbug_header
85 int32_t opcode; member in struct:rbug_proto_header
95 * Get printable string for opcode.
97 const char* rbug_proto_get_name(enum rbug_opcode opcode);
|
| /external/mesa3d/src/gallium/state_trackers/d3d1x/d3d1xshader/src/ |
| sm4_analyze.cpp | 45 switch(program.insns[insn_num]->opcode)
53 check(program.insns[v]->opcode == SM4_OPCODE_LOOP);
67 if(program.insns[insn_num]->opcode == SM4_OPCODE_ELSE)
68 check(program.insns[v]->opcode == SM4_OPCODE_IF);
70 check(program.insns[v]->opcode == SM4_OPCODE_SWITCH || program.insns[v]->opcode == SM4_OPCODE_CASE);
79 if(program.insns[insn_num]->opcode == SM4_OPCODE_ENDIF)
80 check(program.insns[v]->opcode == SM4_OPCODE_IF || program.insns[v]->opcode == SM4_OPCODE_ELSE);
82 check(program.insns[v]->opcode == SM4_OPCODE_SWITCH || program.insns[v]->opcode == SM4_OPCODE_CASE)
[all...] |
| /art/runtime/ |
| dex_instruction.cc | 62 #define INSTRUCTION_SIZE(opcode, c, p, format, r, i, a, v) \
63 ((opcode == NOP) ? -1 : \
75 switch (FormatOf(Opcode())) {
92 Code opcode = static_cast<Code>(insn & 0xFF); local
93 return FlagsOf(opcode) & Instruction::kContinue;
138 const char* opcode = kInstructionNames[Opcode()]; local
139 switch (FormatOf(Opcode())) {
140 case k10x: os << opcode; break; local
141 case k12x: os << StringPrintf("%s v%d, v%d", opcode, VRegA_12x(), VRegB_12x()); break
304 os << opcode << " {"; local
321 os << opcode << " {"; local
334 os << opcode << " {"; local
[all...] |
| /art/compiler/dex/quick/arm/ |
| utility_arm.cc | 224 ArmOpcode opcode = kThumbBkpt; local
227 opcode = kThumbBlxR;
230 opcode = kThumbBx;
233 LOG(FATAL) << "Bad opcode " << op;
235 return NewLIR1(opcode, r_dest_src.GetReg());
242 ArmOpcode opcode = kThumbBkpt; local
245 opcode = (thumb_form) ? kThumbAdcRR : kThumb2AdcRRR;
248 opcode = (thumb_form) ? kThumbAndRR : kThumb2AndRRR;
251 opcode = (thumb_form) ? kThumbBicRR : kThumb2BicRRR;
255 opcode = (thumb_form) ? kThumbCmnRR : kThumb2CmnRR
392 ArmOpcode opcode = kThumbBkpt; local
467 ArmOpcode opcode = kThumbBkpt; local
604 ArmOpcode opcode = kThumbBkpt; local
696 ArmOpcode opcode = kThumbBkpt; local
762 ArmOpcode opcode = kThumbBkpt; local
857 ArmOpcode opcode = kThumbBkpt; local
998 ArmOpcode opcode = kThumbBkpt; local
1142 int opcode; local
[all...] |
| /art/compiler/dex/quick/x86/ |
| x86_lir.h | 385 // MR - Memory Register - opcode [base + disp], reg
387 // AR - Array Register - opcode [base + index * scale + disp], reg
389 // TR - Thread Register - opcode fs:[disp], reg - where fs: is equal to Thread::Current()
391 // RR - Register Register - opcode reg1, reg2
393 // RM - Register Memory - opcode reg, [base + disp]
395 // RA - Register Array - opcode reg, [base + index * scale + disp]
397 // RT - Register Thread - opcode reg, fs:[disp] - where fs: is equal to Thread::Current()
399 // RI - Register Immediate - opcode reg, #immediate
401 // MI - Memory Immediate - opcode [base + disp], #immediate
403 // AI - Array Immediate - opcode [base + index * scale + disp], #immediat
690 X86OpCode opcode; \/\/ e.g. kOpAddRI member in struct:art::X86EncodingMap
698 uint8_t opcode; \/\/ 1 byte opcode. member in struct:art::X86EncodingMap::__anon19
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/r300/compiler/ |
| radeon_swizzle.h | 44 * can be implemented natively by the hardware for this opcode.
46 * \return 1 if the swizzle is native for the given opcode
48 int (*IsNative)(rc_opcode opcode, struct rc_src_register reg);
|
| /external/chromium_org/third_party/yasm/source/patched-yasm/modules/arch/x86/tests/ |
| gen-fma-test.py | 3 def emit(opcode,suffix,width,order,optype):
5 d['opcode']=opcode
29 print "v%(opcode)s%(order)s%(suffix)s %(op1)s, %(op2)s, %(op3)s" % (d)
32 print "v%(opcode)s%(order)s%(suffix)s %(op1)s, %(op2)s, %(op3)s" % (d)
35 for opcode in opcodes:
39 emit(opcode,suffix,width,order,optype)
|
| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| radeon_swizzle.h | 44 * can be implemented natively by the hardware for this opcode.
46 * \return 1 if the swizzle is native for the given opcode
48 int (*IsNative)(rc_opcode opcode, struct rc_src_register reg);
|
| /art/runtime/quick/ |
| inline_method_analyser.h | 109 // The op_variant below is opcode-Instruction::IGET for IGETs and
110 // opcode-Instruction::IPUT for IPUTs. This is because the runtime
133 InlineMethodOpcode opcode; member in struct:art::InlineMethod
155 static constexpr bool IsInstructionIGet(Instruction::Code opcode) {
156 return Instruction::IGET <= opcode && opcode <= Instruction::IGET_SHORT;
159 static constexpr bool IsInstructionIPut(Instruction::Code opcode) {
160 return Instruction::IPUT <= opcode && opcode <= Instruction::IPUT_SHORT;
163 static constexpr uint16_t IGetVariant(Instruction::Code opcode) {
[all...] |
| /dalvik/dx/src/com/android/dx/io/instructions/ |
| SparseSwitchPayloadDecodedInstruction.java | 38 int opcode, int[] keys, int[] targets) {
39 super(format, opcode, 0, null, 0, 0L);
|
| ZeroRegisterDecodedInstruction.java | 28 public ZeroRegisterDecodedInstruction(InstructionCodec format, int opcode,
30 super(format, opcode, index, indexType, target, literal);
|
| /external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/i965/ |
| brw_shader.h | 32 uint32_t brw_math_function(enum opcode op);
|
| /external/dexmaker/src/dx/java/com/android/dx/io/instructions/ |
| SparseSwitchPayloadDecodedInstruction.java | 38 int opcode, int[] keys, int[] targets) {
39 super(format, opcode, 0, null, 0, 0L);
|
| ZeroRegisterDecodedInstruction.java | 28 public ZeroRegisterDecodedInstruction(InstructionCodec format, int opcode,
30 super(format, opcode, index, indexType, target, literal);
|
| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| brw_shader.h | 32 uint32_t brw_math_function(enum opcode op);
|
| /dalvik/dexgen/src/com/android/dexgen/dex/code/ |
| TargetInsn.java | 34 * @param opcode the opcode; one of the constants from {@link Dops}
41 public TargetInsn(Dop opcode, SourcePosition position,
43 super(opcode, position, registers);
54 public DalvInsn withOpcode(Dop opcode) {
55 return new TargetInsn(opcode, getPosition(), getRegisters(), target);
66 * opcode has the opposite sense (as a test; e.g. a
75 Dop opcode = getOpcode().getOppositeTest(); local
77 return new TargetInsn(opcode, getPosition(), getRegisters(), target);
|
| /dalvik/dx/src/com/android/dx/dex/code/ |
| TargetInsn.java | 34 * @param opcode the opcode; one of the constants from {@link Dops}
41 public TargetInsn(Dop opcode, SourcePosition position,
43 super(opcode, position, registers);
54 public DalvInsn withOpcode(Dop opcode) {
55 return new TargetInsn(opcode, getPosition(), getRegisters(), target);
66 * opcode has the opposite sense (as a test; e.g. a
75 Dop opcode = getOpcode().getOppositeTest(); local
77 return new TargetInsn(opcode, getPosition(), getRegisters(), target);
|
| /external/chromium_org/third_party/mesa/src/src/gallium/docs/source/exts/ |
| formatting.py | 20 opcode, desc = sig.split("-", 1)
21 opcode = opcode.strip().upper()
23 signode += sphinx.addnodes.desc_name(opcode, opcode)
25 return opcode
30 app.add_description_unit("opcode", "opcode", "%s (TGSI opcode)",
|
| /external/dexmaker/src/dx/java/com/android/dx/dex/code/ |
| TargetInsn.java | 34 * @param opcode the opcode; one of the constants from {@link Dops}
41 public TargetInsn(Dop opcode, SourcePosition position,
43 super(opcode, position, registers);
54 public DalvInsn withOpcode(Dop opcode) {
55 return new TargetInsn(opcode, getPosition(), getRegisters(), target);
66 * opcode has the opposite sense (as a test; e.g. a
75 Dop opcode = getOpcode().getOppositeTest(); local
77 return new TargetInsn(opcode, getPosition(), getRegisters(), target);
|
| /external/mesa3d/src/gallium/docs/source/exts/ |
| formatting.py | 20 opcode, desc = sig.split("-", 1)
21 opcode = opcode.strip().upper()
23 signode += sphinx.addnodes.desc_name(opcode, opcode)
25 return opcode
30 app.add_description_unit("opcode", "opcode", "%s (TGSI opcode)",
|
| /art/compiler/dex/quick/arm64/ |
| utility_arm64.cc | 91 bool opcode_is_wide = IS_WIDE(lir->opcode);
92 ArmOpcode opcode = UNWIDE(lir->opcode); local
93 DCHECK(!IsPseudoLirOp(opcode));
94 const ArmEncodingMap *encoder = &EncodingMap[opcode];
101 uint64_t check_flags = GetTargetInstFlags(lir->opcode);
334 bool Arm64Mir2Lir::InexpensiveConstantInt(int32_t value, Instruction::Code opcode) {
335 switch (opcode) {
418 ArmOpcode opcode = LIKELY(low_bits == 0) ? kA64Mov2rr : kA64Mvn2rr; local
419 res = NewLIR2(opcode, r_dest.GetReg(), rwzr)
469 ArmOpcode opcode = LIKELY(value == 0) ? WIDE(kA64Mov2rr) : WIDE(kA64Mvn2rr); local
551 ArmOpcode opcode = kA64Brk1d; local
569 ArmOpcode opcode = kA64Brk1d; local
637 ArmOpcode opcode = kA64Brk1d; local
697 ArmOpcode opcode = kA64Brk1d; local
765 ArmOpcode opcode = kA64Brk1d; local
813 ArmOpcode opcode = kA64Brk1d; local
941 ArmOpcode opcode = kA64Brk1d; local
1028 ArmOpcode opcode = kA64Brk1d; local
1116 ArmOpcode opcode = kA64Brk1d; local
1200 ArmOpcode opcode = kA64Brk1d; local
1297 ArmOpcode opcode = kA64Brk1d; local
[all...] |
| /dalvik/dx/src/com/android/dx/rop/code/ |
| PlainInsn.java | 35 * @param opcode {@code non-null;} the opcode
40 public PlainInsn(Rop opcode, SourcePosition position,
42 super(opcode, position, result, sources);
44 switch (opcode.getBranchingness()) {
51 if (result != null && opcode.getBranchingness() != Rop.BRANCH_NONE) {
61 * @param opcode {@code non-null;} the opcode
66 public PlainInsn(Rop opcode, SourcePosition position, RegisterSpec result,
68 this(opcode, position, result, RegisterSpecList.make(source))
130 int opcode = getOpcode().getOpcode(); local
[all...] |
| /external/dexmaker/src/dx/java/com/android/dx/rop/code/ |
| PlainInsn.java | 35 * @param opcode {@code non-null;} the opcode
40 public PlainInsn(Rop opcode, SourcePosition position,
42 super(opcode, position, result, sources);
44 switch (opcode.getBranchingness()) {
51 if (result != null && opcode.getBranchingness() != Rop.BRANCH_NONE) {
61 * @param opcode {@code non-null;} the opcode
66 public PlainInsn(Rop opcode, SourcePosition position, RegisterSpec result,
68 this(opcode, position, result, RegisterSpecList.make(source))
130 int opcode = getOpcode().getOpcode(); local
[all...] |
