Lines Matching refs:r_src
380 LIR* ArmMir2Lir::OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type) {
385 LIR* ArmMir2Lir::OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) {
758 LIR* ArmMir2Lir::StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src,
760 bool all_low_regs = r_base.Low8() && r_index.Low8() && r_src.Low8();
766 if (r_src.IsFloat()) {
767 if (r_src.IsSingle()) {
772 DCHECK(r_src.IsDouble());
774 DCHECK_EQ((r_src.GetReg() & 0x1), 0);
794 store = NewLIR3(opcode, r_src.GetReg(), reg_ptr.GetReg(), 0);
816 store = NewLIR3(opcode, r_src.GetReg(), r_base.GetReg(), r_index.GetReg());
818 store = NewLIR4(opcode, r_src.GetReg(), r_base.GetReg(), r_index.GetReg(), scale);
995 LIR* ArmMir2Lir::StoreBaseDispBody(RegStorage r_base, int displacement, RegStorage r_src,
1001 bool all_low = r_src.Is32Bit() && r_base.Low8() && r_src.Low8();
1008 if (r_src.IsFloat()) {
1009 DCHECK(!r_src.IsPair());
1010 store = LoadStoreUsingInsnWithOffsetImm8Shl2(kThumb2Vstrd, r_base, displacement, r_src);
1012 DCHECK(r_src.IsPair());
1013 store = LoadStoreUsingInsnWithOffsetImm8Shl2(kThumb2StrdI8, r_base, displacement, r_src);
1022 if (r_src.IsFloat()) {
1023 DCHECK(r_src.IsSingle());
1024 store = LoadStoreUsingInsnWithOffsetImm8Shl2(kThumb2Vstrs, r_base, displacement, r_src);
1028 if (r_src.Low8() && (r_base == rs_r13sp) && (displacement <= 1020) && (displacement >= 0)) {
1069 store = NewLIR3(opcode, r_src.GetReg(), r_base.GetReg(), encoded_disp);
1073 DCHECK(!r_src.IsFloat());
1074 store = StoreBaseIndexed(r_base, r_scratch, r_src, 0, size);
1082 AnnotateDalvikRegAccess(store, displacement >> 2, false /* is_load */, r_src.Is64Bit());
1087 LIR* ArmMir2Lir::StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src,
1101 DCHECK(!r_src.IsFloat()); // See RegClassForFieldLoadSave().
1105 // We have only 5 temporary registers available and if r_base, r_src and r_ptr already
1120 NewLIR4(kThumb2Strexd, r_temp.GetReg(), r_src.GetLowReg(), r_src.GetHighReg(), r_ptr.GetReg());
1129 null_ck_insn = StoreBaseDispBody(r_base, displacement, r_src, size);
1141 LIR* ArmMir2Lir::OpFpRegCopy(RegStorage r_dest, RegStorage r_src) {
1143 DCHECK_EQ(r_dest.IsDouble(), r_src.IsDouble());
1148 opcode = r_src.IsSingle() ? kThumb2Vmovs : kThumb2Fmsr;
1150 DCHECK(r_src.IsSingle());
1154 LIR* res = RawLIR(current_dalvik_offset_, opcode, r_dest.GetReg(), r_src.GetReg());
1155 if (!(cu_->disable_opt & (1 << kSafeOptimizations)) && r_dest == r_src) {
