Lines Matching defs:Rn
311 ArmRegister rn(instruction, 16);
312 if (rn.r == 0xf) {
318 args << "[" << rn << ", #" << offset << "]";
320 args << "[" << rn << ", #" << offset << "]!";
322 args << "[" << rn << "], #" << offset;
326 if (rn.r == 9) {
467 // |111|01|00|op|0|WL| Rn | |
476 ArmRegister Rn(instr, 16);
481 args << Rn << (W == 0 ? "" : "!") << ", ";
483 if (Rn.r != 13) {
485 args << Rn << (W == 0 ? "" : "!") << ", ";
492 if (Rn.r != 13) {
494 args << Rn << (W == 0 ? "" : "!") << ", ";
500 args << Rn << (W == 0 ? "" : "!") << ", ";
509 ArmRegister Rn(instr, 16);
523 args << Rt << "," << Rd << ", [" << Rn;
538 args << Rd << ", " << Rt << ", [" << Rn << ", #" << (imm8 << 2) << "]";
539 if (Rd.r == 13 || Rd.r == 15 || Rt.r == 13 || Rt.r == 15 || Rn.r == 15 ||
540 Rd.r == Rn.r || Rd.r == Rt.r) {
551 args << Rd << ", " << Rt << ", [" << Rn << "]";
552 if (Rd.r == 13 || Rd.r == 15 || Rt.r == 13 || Rt.r == 15 || Rn.r == 15 ||
553 Rd.r == Rn.r || Rd.r == Rt.r || (instr & 0xf00) != 0xf00) {
561 args << Rd << ", " << Rt << ", " << Rt2 << ", [" << Rn << "]";
563 Rt2.r == 13 || Rt2.r == 15 || Rn.r == 15 ||
564 Rd.r == Rn.r || Rd.r == Rt.r || Rd.r == Rt2.r) {
574 args << Rt << ", [" << Rn << ", #" << (imm8 << 2) << "]";
575 if (Rt.r == 13 || Rt.r == 15 || Rn.r == 15 || (instr & 0xf00) != 0xf00) {
591 args << Rt << ", [" << Rn << "]";
592 if (Rt.r == 13 || Rt.r == 15 || Rn.r == 15 || (instr & 0xf0f) != 0xf0f) {
598 args << Rt << ", " << Rd /* Rt2 */ << ", [" << Rn << "]";
600 Rn.r == 15 || (instr & 0x00f) != 0x00f) {
618 args << Rt << "," << Rd << ", [" << Rn;
640 // |111|0101| op3|S| Rn |imm3| Rd |i2|ty| Rm |
648 ArmRegister Rn(instr, 16);
665 if (Rn.r != 0xF) {
673 if (Rn.r != 0xF) {
730 if (Rn.r != 0xF) {
731 args << Rn << ", ";
764 // |111| |11| op3 | Rn | |copr| |op4| |
778 // |1110|110|PUDWL| Rn | Vd |101|S| imm8 |
787 ArmRegister Rn(instr, 16);
792 args << d << ", [" << Rn << ", #" << ((U == 1) ? "" : "-")
794 if (Rn.r == 15 && U == 1) {
800 } else if (Rn.r == 13 && W == 1 && U == L) { // VPUSH/VPOP
805 args << Rn << ((W == 1) ? "!" : "") << ", "
1030 // |111|10|i0| op3|S| Rn |0|iii| Rd |iiiiiiii|
1035 ArmRegister Rn(instr, 16);
1040 if (Rn.r == 0xF && (op3 == 0x2 || op3 == 0x3)) {
1065 args << Rn << ", #" << ThumbExpand(imm32);
1083 args << Rd << ", " << Rn << ", #" << ThumbExpand(imm32);
1093 // |111|10|x1| op3 | Rn |0|xxxxxxxxxxxxxxx|
1097 // ADD/SUB.W Rd, Rn #imm12 - 111 10 i1 0101 0 nnnn 0 iii dddd iiiiiiii
1099 ArmRegister Rn(instr, 16);
1104 if (Rn.r != 0xF) {
1106 args << Rd << ", " << Rn << ", #" << imm12;
1120 uint32_t Rn = (instr >> 16) & 0xF;
1121 uint32_t imm16 = (Rn << 12) | (i << 11) | (imm3 << 8) | imm8;
1127 // BFI Rd, Rn, #lsb, #width - 111 10 0 11 011 0 nnnn 0 iii dddd ii 0 iiiii
1129 ArmRegister Rn(instr, 16);
1135 if (Rn.r != 0xF) {
1137 args << Rd << ", " << Rn << ", #" << lsb << ", #" << width;
1280 // {ST,LD}RB Rt,[Rn,#+/-imm12] - 111 11 00 0 1 00 0 nnnn tttt 1 PUWii ii iiii
1281 // {ST,LD}RB Rt,[Rn,#+/-imm8] - 111 11 00 0 0 00 0 nnnn tttt 1 PUWii ii iiii
1282 // {ST,LD}RB Rt,[Rn,Rm,lsl #imm2] - 111 11 00 0 0 00 0 nnnn tttt 0 00000 ii mmmm
1283 ArmRegister Rn(instr, 16);
1288 args << Rt << ", [" << Rn << ",#" << imm12 << "]";
1291 args << Rt << ", [" << Rn << ",#" << imm8 << "]";
1295 args << Rt << ", [" << Rn << ", " << Rm;
1304 // STRH Rt,[Rn,#+/-imm12] - 111 11 00 0 1 01 0 nnnn tttt 1 PUWii ii iiii
1305 // STRH Rt,[Rn,#+/-imm8] - 111 11 00 0 0 01 0 nnnn tttt 1 PUWii ii iiii
1306 // STRH Rt,[Rn,Rm,lsl #imm2] - 111 11 00 0 0 01 0 nnnn tttt 0 00000 ii mmmm
1307 ArmRegister Rn(instr, 16);
1312 args << Rt << ", [" << Rn << ",#" << imm12 << "]";
1315 args << Rt << ", [" << Rn << ",#" << imm8 << "]";
1319 args << Rt << ", [" << Rn << ", " << Rm;
1328 ArmRegister Rn(instr, 16);
1332 // STR Rt, [Rn, #imm8] - 111 11 000 010 0 nnnn tttt 1PUWiiiiiiii
1338 if (Rn.r == 13 && P == 1 && U == 0 && W == 1 && imm32 == 4) {
1341 } else if (Rn.r == 15 || (P == 0 && W == 0)) {
1349 args << Rt << ", [" << Rn;
1360 // STR Rt, [Rn, Rm, LSL #imm2] - 111 11 000 010 0 nnnn tttt 000000iimmmm
1361 ArmRegister Rn(instr, 16);
1366 args << Rt << ", [" << Rn << ", " << Rm;
1373 // STR.W Rt, [Rn, #imm12] - 111 11 000 110 0 nnnn tttt iiiiiiiiiiii
1376 args << Rt << ", [" << Rn << ", #" << imm12 << "]";
1392 // |111|11|00|op3|01|1| Rn | Rt | op4 | |
1395 ArmRegister Rn(instr, 16);
1399 // LDRH.W Rt, [Rn, #imm12] - 111 11 00 01 011 nnnn tttt iiiiiiiiiiii
1402 args << Rt << ", [" << Rn << ", #" << imm12 << "]";
1403 if (Rn.r == 9) {
1406 } else if (Rn.r == 15) {
1412 // LDRSH.W Rt, [Rn, #imm12] - 111 11 00 11 011 nnnn tttt iiiiiiiiiiii
1413 // LDRSB.W Rt, [Rn, #imm12] - 111 11 00 11 001 nnnn tttt iiiiiiiiiiii
1416 args << Rt << ", [" << Rn << ", #" << imm12 << "]";
1417 if (Rn.r == 9) {
1420 } else if (Rn.r == 15) {
1462 // |111|11|00|op3|10|1| Rn | Rt | op4 | |
1466 ArmRegister Rn(instr, 16);
1468 if (op3 == 1 || Rn.r == 15) {
1469 // LDR.W Rt, [Rn, #imm12] - 111 11 00 00 101 nnnn tttt iiiiiiiiiiii
1473 args << Rt << ", [" << Rn << ", #" << imm12 << "]";
1474 if (Rn.r == 9) {
1477 } else if (Rn.r == 15) {
1483 // LDR.W Rt, [Rn, Rm{, LSL #imm2}] - 111 11 00 00 101 nnnn tttt 000000iimmmm
1487 args << Rt << ", [" << Rn << ", " << rm;
1497 // LDRT Rt, [Rn, #imm8] - 111 11 00 00 101 nnnn tttt 1110iiiiiiii
1500 args << Rt << ", [" << Rn << ", #" << imm8 << "]";
1501 } else if (Rn.r == 13 && !p && u && w && (instr & 0xff) == 4) {
1511 args << "[" << Rn << ", #" << offset << "]";
1513 args << "[" << Rn << ", #" << offset << "]!";
1515 args << "[" << Rn << "], #" << offset;
1531 ArmRegister Rn(instr, 16);
1534 args << Rd << ", " << Rn << ", " << Rm;
1541 ArmRegister Rn(instr, 16);
1549 args << Rd << ", " << Rn << ", " << Rm;
1552 args << Rd << ", " << Rn << ", " << Rm << ", " << Ra;
1556 args << Rd << ", " << Rn << ", " << Rm << ", " << Ra;
1571 ArmRegister Rn(instr, 16);
1579 args << RdLo << ", " << RdHi << ", " << Rn << ", " << Rm;
1583 args << Rd << ", " << Rn << ", " << Rm;
1587 args << RdLo << ", " << RdHi << ", " << Rn << ", " << Rm;
1591 args << Rd << ", " << Rn << ", " << Rm;
1656 ThumbRegister Rn(instr, 3);
1667 args << Rd << ", " << Rn;
1681 // CMP Rn, #imm8 - 00101 nnn iiiiiiii
1682 // ADDS Rn, #imm8 - 00110 nnn iiiiiiii
1683 // SUBS Rn, #imm8 - 00111 nnn iiiiiiii
1684 ThumbRegister Rn(instr, 8);
1692 args << Rn << ", #" << imm8;
1735 uint16_t Rn = instr & 7;
1736 ArmRegister N_Rn((N << 3) | Rn);
1765 ThumbRegister Rn(instr, 3);
1777 args << Rt << ", [" << Rn << ", " << Rm << "]";
1787 ThumbRegister Rn(instr, 3);
1803 args << Rt << ", [" << Rn << ", #" << imm5 << "]";
1841 ThumbRegister Rn(instr, 0);
1844 args << Rn << ", ";
1908 // STR Rt, [Rn, #imm] - 01100 iiiii nnn ttt
1909 // LDR Rt, [Rn, #imm] - 01101 iiiii nnn ttt
1911 ThumbRegister Rn(instr, 3);
1914 args << Rt << ", [" << Rn << ", #" << (imm5 << 2) << "]";
