Lines Matching defs:Rt
510 ArmRegister Rt(instr, 12);
523 args << Rt << "," << Rd << ", [" << Rn;
538 args << Rd << ", " << Rt << ", [" << Rn << ", #" << (imm8 << 2) << "]";
539 if (Rd.r == 13 || Rd.r == 15 || Rt.r == 13 || Rt.r == 15 || Rn.r == 15 ||
540 Rd.r == Rn.r || Rd.r == Rt.r) {
551 args << Rd << ", " << Rt << ", [" << Rn << "]";
552 if (Rd.r == 13 || Rd.r == 15 || Rt.r == 13 || Rt.r == 15 || Rn.r == 15 ||
553 Rd.r == Rn.r || Rd.r == Rt.r || (instr & 0xf00) != 0xf00) {
561 args << Rd << ", " << Rt << ", " << Rt2 << ", [" << Rn << "]";
562 if (Rd.r == 13 || Rd.r == 15 || Rt.r == 13 || Rt.r == 15 ||
564 Rd.r == Rn.r || Rd.r == Rt.r || Rd.r == Rt2.r) {
574 args << Rt << ", [" << Rn << ", #" << (imm8 << 2) << "]";
575 if (Rt.r == 13 || Rt.r == 15 || Rn.r == 15 || (instr & 0xf00) != 0xf00) {
591 args << Rt << ", [" << Rn << "]";
592 if (Rt.r == 13 || Rt.r == 15 || Rn.r == 15 || (instr & 0xf0f) != 0xf0f) {
598 args << Rt << ", " << Rd /* Rt2 */ << ", [" << Rn << "]";
599 if (Rt.r == 13 || Rt.r == 15 || Rd.r == 13 /* Rt2 */ || Rd.r == 15 /* Rt2 */ ||
618 args << Rt << "," << Rd << ", [" << Rn;
816 ArmRegister Rt(instr, 12);
820 args << Rt << ", " << Rt2 << ", ";
828 args << ", " << Rt << ", " << Rt2;
830 if (Rt.r == 15 || Rt.r == 13 || Rt2.r == 15 || Rt2.r == 13 ||
831 (S == 0 && m.r == 31) || (L == 1 && Rt.r == Rt2.r)) {
978 // |1110|1110|000|op| Vn | Rt |1010|N|00|1|0000|
980 ArmRegister Rt(instr, 12);
984 args << Rt << ", " << n;
986 args << n << ", " << Rt;
988 if (Rt.r == 13 || Rt.r == 15 || (instr & 0x6F) != 0) {
999 // |1110|11101111|reg | Rt |1010|000|1|0000| - last 7 0s are (0)
1001 ArmRegister Rt(instr, 12);
1004 if (Rt.r == 15) {
1006 } else if (Rt.r == 13) {
1007 args << Rt << ", FPSCR (UNPREDICTABLE)";
1009 args << Rt << ", FPSCR";
1280 // {ST,LD}RB Rt,[Rn,#+/-imm12] - 111 11 00 0 1 00 0 nnnn tttt 1 PUWii ii iiii
1281 // {ST,LD}RB Rt,[Rn,#+/-imm8] - 111 11 00 0 0 00 0 nnnn tttt 1 PUWii ii iiii
1282 // {ST,LD}RB Rt,[Rn,Rm,lsl #imm2] - 111 11 00 0 0 00 0 nnnn tttt 0 00000 ii mmmm
1284 ArmRegister Rt(instr, 12);
1288 args << Rt << ", [" << Rn << ",#" << imm12 << "]";
1291 args << Rt << ", [" << Rn << ",#" << imm8 << "]";
1295 args << Rt << ", [" << Rn << ", " << Rm;
1304 // STRH Rt,[Rn,#+/-imm12] - 111 11 00 0 1 01 0 nnnn tttt 1 PUWii ii iiii
1305 // STRH Rt,[Rn,#+/-imm8] - 111 11 00 0 0 01 0 nnnn tttt 1 PUWii ii iiii
1306 // STRH Rt,[Rn,Rm,lsl #imm2] - 111 11 00 0 0 01 0 nnnn tttt 0 00000 ii mmmm
1308 ArmRegister Rt(instr, 12);
1312 args << Rt << ", [" << Rn << ",#" << imm12 << "]";
1315 args << Rt << ", [" << Rn << ",#" << imm8 << "]";
1319 args << Rt << ", [" << Rn << ", " << Rm;
1329 ArmRegister Rt(instr, 12);
1332 // STR Rt, [Rn, #imm8] - 111 11 000 010 0 nnnn tttt 1PUWiiiiiiii
1340 args << "{" << Rt << "}";
1349 args << Rt << ", [" << Rn;
1360 // STR Rt, [Rn, Rm, LSL #imm2] - 111 11 000 010 0 nnnn tttt 000000iimmmm
1362 ArmRegister Rt(instr, 12);
1366 args << Rt << ", [" << Rn << ", " << Rm;
1373 // STR.W Rt, [Rn, #imm12] - 111 11 000 110 0 nnnn tttt iiiiiiiiiiii
1376 args << Rt << ", [" << Rn << ", #" << imm12 << "]";
1392 // |111|11|00|op3|01|1| Rn | Rt | op4 | |
1396 ArmRegister Rt(instr, 12);
1397 if (Rt.r != 15) {
1399 // LDRH.W Rt, [Rn, #imm12] - 111 11 00 01 011 nnnn tttt iiiiiiiiiiii
1402 args << Rt << ", [" << Rn << ", #" << imm12 << "]";
1412 // LDRSH.W Rt, [Rn, #imm12] - 111 11 00 11 011 nnnn tttt iiiiiiiiiiii
1413 // LDRSB.W Rt, [Rn, #imm12] - 111 11 00 11 001 nnnn tttt iiiiiiiiiiii
1416 args << Rt << ", [" << Rn << ", #" << imm12 << "]";
1462 // |111|11|00|op3|10|1| Rn | Rt | op4 | |
1467 ArmRegister Rt(instr, 12);
1469 // LDR.W Rt, [Rn, #imm12] - 111 11 00 00 101 nnnn tttt iiiiiiiiiiii
1470 // LDR.W Rt, [PC, #imm12] - 111 11 00 0x 101 1111 tttt iiiiiiiiiiii
1473 args << Rt << ", [" << Rn << ", #" << imm12 << "]";
1483 // LDR.W Rt, [Rn, Rm{, LSL #imm2}] - 111 11 00 00 101 nnnn tttt 000000iimmmm
1487 args << Rt << ", [" << Rn << ", " << rm;
1497 // LDRT Rt, [Rn, #imm8] - 111 11 00 00 101 nnnn tttt 1110iiiiiiii
1500 args << Rt << ", [" << Rn << ", #" << imm8 << "]";
1504 args << "{" << Rt << "}";
1509 args << Rt << ",";
1753 ThumbRegister Rt(instr, 8);
1756 args << Rt << ", [pc, #" << (imm8 << 2) << "]";
1766 ThumbRegister Rt(instr, 0);
1777 args << Rt << ", [" << Rn << ", " << Rm << "]";
1780 ThumbRegister Rt(instr, 8);
1783 args << Rt << ", [sp, #" << (imm8 << 2) << "]";
1788 ThumbRegister Rt(instr, 0);
1803 args << Rt << ", [" << Rn << ", #" << imm5 << "]";
1908 // STR Rt, [Rn, #imm] - 01100 iiiii nnn ttt
1909 // LDR Rt, [Rn, #imm] - 01101 iiiii nnn ttt
1912 ThumbRegister Rt(instr, 0);
1914 args << Rt << ", [" << Rn << ", #" << (imm5 << 2) << "]";
1918 // STR Rt, [SP, #imm] - 01100 ttt iiiiiiii
1919 // LDR Rt, [SP, #imm] - 01101 ttt iiiiiiii
1921 ThumbRegister Rt(instr, 8);
1923 args << Rt << ", [sp, #" << (imm8 << 2) << "]";
