Lines Matching defs:Rn
754 FPSCR_rounding_mode_ = RN;
1532 int rn = instr->RnValue();
1533 int32_t rn_val = get_register(rn);
2009 int rn = instr->RnValue();
2018 // Rn field to encode it.
2019 // Format(instr, "mul'cond's 'rn, 'rm, 'rs");
2020 int rd = rn; // Remap the rn field to the Rd register.
2031 // of registers as "Rd, Rm, Rs, Rn". But confusingly it uses the
2032 // Rn field to encode the Rd register and the Rd field to encode
2033 // the Rn register.
2034 // Format(instr, "mla'cond's 'rn, 'rm, 'rs, 'rd");
2037 set_register(rn, result);
2039 // Format(instr, "mls'cond's 'rn, 'rm, 'rs, 'rd");
2042 set_register(rn, result);
2047 // when referring to the target registers. They are mapped to the Rn
2050 // RdHi == Rn (This is confusingly stored in variable rd here
2052 // Rn field to encode the Rd register. Good luck figuring
2055 // Format(instr, "'um'al'cond's 'rd, 'rn, 'rs, 'rm");
2056 int rd_hi = rn; // Remap the rn field to the RdHi register.
2086 int rn = instr->RnValue();
2087 int32_t rn_val = get_register(rn);
2094 // Format(instr, "'memop'cond'sign'h 'rd, ['rn], -'rm");
2098 set_register(rn, rn_val);
2102 // Format(instr, "'memop'cond'sign'h 'rd, ['rn], +'rm");
2106 set_register(rn, rn_val);
2110 // Format(instr, "'memop'cond'sign'h 'rd, ['rn, -'rm]'w");
2114 set_register(rn, rn_val);
2119 // Format(instr, "'memop'cond'sign'h 'rd, ['rn, +'rm]'w");
2123 set_register(rn, rn_val);
2137 // Format(instr, "'memop'cond'sign'h 'rd, ['rn], #-'off8");
2141 set_register(rn, rn_val);
2145 // Format(instr, "'memop'cond'sign'h 'rd, ['rn], #+'off8");
2149 set_register(rn, rn_val);
2153 // Format(instr, "'memop'cond'sign'h 'rd, ['rn, #-'off8]'w");
2157 set_register(rn, rn_val);
2162 // Format(instr, "'memop'cond'sign'h 'rd, ['rn, #+'off8]'w");
2166 set_register(rn, rn_val);
2267 int rn = instr->RnValue();
2268 int32_t rn_val = get_register(rn);
2281 // Format(instr, "and'cond's 'rd, 'rn, 'shift_rm");
2282 // Format(instr, "and'cond's 'rd, 'rn, 'imm");
2293 // Format(instr, "eor'cond's 'rd, 'rn, 'shift_rm");
2294 // Format(instr, "eor'cond's 'rd, 'rn, 'imm");
2305 // Format(instr, "sub'cond's 'rd, 'rn, 'shift_rm");
2306 // Format(instr, "sub'cond's 'rd, 'rn, 'imm");
2318 // Format(instr, "rsb'cond's 'rd, 'rn, 'shift_rm");
2319 // Format(instr, "rsb'cond's 'rd, 'rn, 'imm");
2331 // Format(instr, "add'cond's 'rd, 'rn, 'shift_rm");
2332 // Format(instr, "add'cond's 'rd, 'rn, 'imm");
2344 // Format(instr, "adc'cond's 'rd, 'rn, 'shift_rm");
2345 // Format(instr, "adc'cond's 'rd, 'rn, 'imm");
2357 Format(instr, "sbc'cond's 'rd, 'rn, 'shift_rm");
2358 Format(instr, "sbc'cond's 'rd, 'rn, 'imm");
2363 Format(instr, "rsc'cond's 'rd, 'rn, 'shift_rm");
2364 Format(instr, "rsc'cond's 'rd, 'rn, 'imm");
2370 // Format(instr, "tst'cond 'rn, 'shift_rm");
2371 // Format(instr, "tst'cond 'rn, 'imm");
2385 // Format(instr, "teq'cond 'rn, 'shift_rm");
2386 // Format(instr, "teq'cond 'rn, 'imm");
2400 // Format(instr, "cmp'cond 'rn, 'shift_rm");
2401 // Format(instr, "cmp'cond 'rn, 'imm");
2417 // Format(instr, "cmn'cond 'rn, 'shift_rm");
2418 // Format(instr, "cmn'cond 'rn, 'imm");
2432 // Format(instr, "orr'cond's 'rd, 'rn, 'shift_rm");
2433 // Format(instr, "orr'cond's 'rd, 'rn, 'imm");
2456 // Format(instr, "bic'cond's 'rd, 'rn, 'shift_rm");
2457 // Format(instr, "bic'cond's 'rd, 'rn, 'imm");
2490 int rn = instr->RnValue();
2491 int32_t rn_val = get_register(rn);
2496 // Format(instr, "'memop'cond'b 'rd, ['rn], #-'off12");
2500 set_register(rn, rn_val);
2504 // Format(instr, "'memop'cond'b 'rd, ['rn], #+'off12");
2508 set_register(rn, rn_val);
2512 // Format(instr, "'memop'cond'b 'rd, ['rn, #-'off12]'w");
2516 set_register(rn, rn_val);
2521 // Format(instr, "'memop'cond'b 'rd, ['rn, #+'off12]'w");
2525 set_register(rn, rn_val);
2554 int rn = instr->RnValue();
2555 int32_t rn_val = get_register(rn);
2562 Format(instr, "'memop'cond'b 'rd, ['rn], -'shift_rm");
2576 uint32_t rn_val = get_register(rn);
2583 uint32_t rn_val = get_register(rn);
2684 uint32_t rn_val = get_register(rn);
2716 // (s/u)div (in V8 notation matching ARM ISA format) rn = rm/rs
2717 // Format(instr, "'(s/u)div'cond'b 'rn, 'rm, 'rs);
2733 set_register(rn, ret_val);
2738 // Format(instr, "'memop'cond'b 'rd, ['rn, -'shift_rm]'w");
2741 set_register(rn, addr);
2792 // Format(instr, "'memop'cond'b 'rd, ['rn, +'shift_rm]'w");
2795 set_register(rn, addr);
2826 // Format(instr, "ldm'cond'pu 'rn'w, 'rlist");
2829 // Format(instr, "stm'cond'pu 'rn'w, 'rlist");
3175 DCHECK((mode == RN) || (mode == RM) || (mode == RZ));
3188 case RN:
3254 DCHECK((mode == RM) || (mode == RZ) || (mode == RN));
3277 case RN: {
3346 int rn = instr->RnValue();
3353 int32_t address = get_register(rn) + 4 * offset;
3383 int rn = instr->RnValue();
3390 set_register(rn, data[1]);
3392 int32_t data[] = { get_register(rt), get_register(rn) };
3403 int rn = instr->RnValue();
3409 int32_t address = get_register(rn) + 4 * offset;
3501 int Rn = instr->VnValue();
3504 int32_t address = get_register(Rn);
3534 set_register(Rn, address);
3536 set_register(Rn, get_register(Rn) + get_register(Rm));
3542 int Rn = instr->VnValue();
3545 int32_t address = get_register(Rn);
3575 set_register(Rn, address);
3577 set_register(Rn, get_register(Rn) + get_register(Rm));
