Lines Matching defs:Rn
943 // d = UInt(Rdm); n = UInt(Rn); m = UInt(Rdm); setflags = !InITBlock();
956 // d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); setflags = FALSE;
969 // d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); setflags = (S == '1');
1906 uint32_t Rn; // This function assumes Rn is the SP, but we should verify that.
1915 Rn = Bits32 (opcode, 19, 16);
1917 if (Rn != 13) // 13 is the SP reg on ARM. Verify that Rn == SP.
1924 if (wback && ((Rn == 15) || (Rn == Rt)))
2337 // Read the register value from the operand register Rn.
2391 uint32_t Rn; // the base register which contains the address of the table of branch lengths
2396 Rn = Bits32(opcode, 19, 16);
2399 if (Rn == 13 || BadReg(Rm))
2408 // Read the address of the table from the operand register Rn.
2475 // d = UInt(Rd); n = UInt(Rn); setflags = !InITBlock(); imm32 = ZeroExtend(imm3, 32);
2494 // if Rn == '1101' then SEE ADD (SP plus immediate);
2495 // d = UInt(Rd); n = UInt(Rn); setflags = (S == '1'); imm32 = ThumbExpandImm(i:imm3:imm8);
2509 // if Rn == '1111' then SEE ADR;
2510 // if Rn == '1101' then SEE ADD (SP plus immediate);
2511 // d = UInt(Rd); n = UInt(Rn); setflags = FALSE; imm32 = ZeroExtend(i:imm3:imm8, 32);
2530 uint64_t Rn = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
2535 AddWithCarryResult res = AddWithCarry (Rn, imm32, 0);
2582 uint32_t Rd, Rn;
2583 uint32_t imm32; // the immediate value to be added to the value obtained from Rn
2589 Rn = Bits32(opcode, 19, 16);
2598 uint32_t val1 = ReadCoreReg(Rn, &success);
2607 GetRegisterInfo (eRegisterKindDWARF, Rn, dwarf_reg);
2642 uint32_t Rd, Rn, Rm;
2650 Rn = Bits32(opcode, 5, 3);
2657 Rd = Rn = Bit32(opcode, 7) << 3 | Bits32(opcode, 2, 0);
2662 if (Rn == 15 && Rm == 15)
2669 Rn = Bits32(opcode, 19, 16);
2679 uint32_t val1 = ReadCoreReg(Rn, &success);
2697 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + Rn, op1_reg);
2725 uint32_t Rn; // the first operand
2729 Rn = Bits32(opcode, 19, 16);
2731 if (Rn == 15)
2735 Rn = Bits32(opcode, 19, 16);
2741 // Read the register value from the operand register Rn.
2742 uint32_t reg_val = ReadCoreReg(Rn, &success);
2776 uint32_t Rn; // the first operand
2782 Rn = Bits32(opcode, 2, 0);
2788 Rn = Bits32(opcode, 19, 16);
2792 if (Rn == 15 || BadReg(Rm))
2796 Rn = Bits32(opcode, 19, 16);
2803 // Read the register value from register Rn.
2804 uint32_t val1 = ReadCoreReg(Rn, &success);
2845 uint32_t Rn; // the first operand
2849 Rn = Bits32(opcode, 10, 8);
2853 Rn = Bits32(opcode, 19, 16);
2855 if (Rn == 15)
2859 Rn = Bits32(opcode, 19, 16);
2865 // Read the register value from the operand register Rn.
2866 uint32_t reg_val = ReadCoreReg(Rn, &success);
2900 uint32_t Rn; // the first operand
2906 Rn = Bits32(opcode, 2, 0);
2912 Rn = Bit32(opcode, 7) << 3 | Bits32(opcode, 2, 0);
2916 if (Rn < 8 && Rm < 8)
2918 if (Rn == 15 || Rm == 15)
2922 Rn = Bits32(opcode, 19, 16);
2929 // Read the register value from register Rn.
2930 uint32_t val1 = ReadCoreReg(Rn, &success);
3279 uint32_t Rn; // the first operand register
3286 Rn = Rd;
3292 Rn = Bits32(opcode, 19, 16);
3295 if (BadReg(Rd) || BadReg(Rn) || BadReg(Rm))
3300 Rn = Bits32(opcode, 3, 0);
3303 if (Rd == 15 || Rn == 15 || Rm == 15)
3311 uint32_t value = ReadCoreReg (Rn, &success);
3371 // n = UInt(Rn); registers = '00000000':register_list; wback = (registers<n> == '0');
3381 // if W == '1' && Rn == '1101' then SEE POP;
3382 // n = UInt(Rn); registers = P:M:'0':register_list; wback = (W == '1');
3519 // n = UInt(Rn); registers = register_list; wback = (W == '1');
3536 addr_t Rn = ReadCoreReg (n, &success);
3541 addr_t address = Rn - (addr_byte_size * BitCount (registers)) + addr_byte_size;
3556 context.SetRegisterPlusOffset (dwarf_reg, Rn - (address + offset));
3588 addr_t addr = Rn + offset;
3633 // n = UInt(Rn); registers = P:M:'0':register_list; wback = (W == '1');
3656 // n = UInt(Rn); registers = register_list; wback = (W == '1');
3674 addr_t Rn = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
3679 addr_t address = Rn - (addr_byte_size * BitCount (registers));
3684 context.SetRegisterPlusOffset (dwarf_reg, Rn - address);
3691 context.SetRegisterPlusOffset (dwarf_reg, Rn - (address + offset));
3725 addr_t addr = Rn + offset;
3769 // n = UInt(Rn); registers = register_list; wback = (W == '1');
3785 addr_t Rn = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
3790 addr_t address = Rn + addr_byte_size;
3838 addr_t addr = Rn + offset;
3878 uint32_t Rn; // the base register
3887 Rn = Bits32(opcode, 5, 3);
3899 Rn = 13;
3910 // if Rn == '1111' then SEE LDR (literal);
3911 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32);
3913 Rn = Bits32 (opcode, 19, 16);
3928 // if Rn == '1111' then SEE LDR (literal);
3930 // if Rn == '1101' && P == '0' && U == '1' && W == '1' && imm8 == '00000100' then SEE POP;
3935 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm8, 32);
3937 Rn = Bits32 (opcode, 19, 16);
3946 if ((wback && (Rn == Rt)) || ((Rt == 15) && InITBlock() && !LastInITBlock()))
3954 uint32_t base = ReadCoreReg (Rn, &success);
3965 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + Rn, base_reg);
3972 if (!WriteRegisterUnsigned (ctx, eRegisterKindDWARF, dwarf_r0 + Rn, offset_addr))
4044 // n = UInt(Rn); registers = '00000000':register_list; wback = TRUE;
4057 // n = UInt(Rn); registers = '0':M:'0':register_list; wback = (W == '1');
4074 // n = UInt(Rn); registers = register_list; wback = (W == '1');
4199 // n = UInt(Rn); registers = register_list; wback = (W == '1');
4214 addr_t Rn = ReadCoreReg (n, &success);
4218 addr_t address = Rn - (addr_byte_size * BitCount (registers)) + 4;
4247 context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, Rn - (address + offset));
4278 addr_t data = Rn + offset;
4325 // if W == '1' && Rn == '1101' then SEE PUSH;
4330 // n = UInt(Rn); registers = '0':M:'0':register_list; wback = (W == '1');
4344 // if W == '1' && Rn == '1101? && BitCount(register_list) >= 2 then SEE PUSH;
4349 // n = UInt(Rn); registers = register_list; wback = (W == '1');
4365 addr_t Rn = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
4369 addr_t address = Rn - (addr_byte_size * BitCount (registers));
4398 context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, Rn - (address + offset));
4429 addr_t data = Rn + offset;
4475 // n = UInt(Rn); registers = register_list; wback = (W == '1');
4490 addr_t Rn = ReadCoreReg (n, &success);
4494 addr_t address = Rn + addr_byte_size;
4555 addr_t data = Rn + offset;
4596 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm5:'00', 32);
4620 // if Rn == '1111' then UNDEFINED;
4624 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32);
4641 // if Rn
4642 // if Rn == '1111' || (P == '0' && W == '0') then UNDEFINED;
4647 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm8, 32);
4765 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
4781 // if Rn == '1111' then UNDEFINED;
4785 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
4807 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
4942 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm5, 32);
4954 // if Rn == '1111' then UNDEFINED;
4958 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32);
4975 // if Rn == '1111' || (P == '0' && W == '0') then UNDEFINED;
4979 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm8, 32);
5086 Rn); m = UInt(Rm);
5103 // if Rn == '1111' then UNDEFINED;
5104 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
5128 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
5160 uint32_t Rn = ReadCoreReg (n, &success);
5172 offset_addr = Rn + offset;
5174 offset_addr = Rn - offset;
5181 address = Rn;
5255 uint32_t Rd, Rn;
5256 uint32_t imm32; // the immediate value to be added to the value obtained from Rn
5262 Rn = Bits32(opcode, 19, 16);
5265 if (BadReg(Rd) || BadReg(Rn))
5270 Rn = Bits32(opcode, 19, 16);
5282 int32_t val1 = ReadCoreReg(Rn, &success);
5325 uint32_t Rd, Rn, Rm;
5332 Rd = Rn = Bits32(opcode, 2, 0);
5340 Rn = Bits32(opcode, 19, 16);
5344 if (BadReg(Rd) || BadReg(Rn) || BadReg(Rm))
5349 Rn = Bits32(opcode, 19, 16);
5362 int32_t val1 = ReadCoreReg(Rn, &success);
5476 uint32_t Rd, Rn;
5477 uint32_t imm32; // the immediate value to be ANDed to the value obtained from Rn
5484 Rn = Bits32(opcode, 19, 16);
5490 if (Rd == 13 || (Rd == 15 && !setflags) || BadReg(Rn))
5495 Rn = Bits32(opcode, 19, 16);
5507 uint32_t val1 = ReadCoreReg(Rn, &success);
5550 uint32_t Rd, Rn, Rm;
5558 Rd = Rn = Bits32(opcode, 2, 0);
5566 Rn = Bits32(opcode, 19, 16);
5573 if (Rd == 13 || (Rd == 15 && !setflags) || BadReg(Rn) || BadReg(Rm))
5578 Rn = Bits32(opcode, 19, 16);
5591 uint32_t val1 = ReadCoreReg(Rn, &success);
5641 uint32_t Rd, Rn;
5642 uint32_t imm32; // the immediate value to be bitwise inverted and ANDed to the value obtained from Rn
5649 Rn = Bits32(opcode, 19, 16);
5652 if (BadReg(Rd) || BadReg(Rn))
5657 Rn = Bits32(opcode, 19, 16);
5670 uint32_t val1 = ReadCoreReg(Rn, &success);
5713 uint32_t Rd, Rn, Rm;
5721 Rd = Rn = Bits32(opcode, 2, 0);
5729 Rn = Bits32(opcode, 19, 16);
5733 if (BadReg(Rd) || BadReg(Rn) || BadReg(Rm))
5738 Rn = Bits32(opcode, 19, 16);
5752 uint32_t val1 = ReadCoreReg(Rn, &success);
5812 // if Rn == '1111' then SEE LDR (literal);
5814 // if Rn == '1101' && P == '0' && U == '1' && W == '0' && imm12 == '000000000100' then SEE POP;
5815 // t == UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32);
5958 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
5975 // if Rn == '1111' then SEE LDR (literal);
5976 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
6003 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
6037 uint32_t Rn = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
6051 offset_addr = Rn + offset;
6053 offset_addr = Rn - offset;
6059 address = Rn;
6067 context.SetRegisterPlusOffset (base_reg, address - Rn);
6089 context.SetRegisterPlusOffset (base_reg, address - Rn);
6100 context.SetRegisterPlusOffset (base_reg, address - Rn);
6156 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm5, 32);
6170 // if Rn == '1111' then SEE LDRB (literal);
6171 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32);
6189 // if Rn == '1111' then SEE LDRB (literal);
6195 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm8, 32);
6215 uint32_t Rn = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
6224 offset_addr = Rn + imm32;
6226 offset_addr = Rn - imm32;
6232 address = Rn;
6242 context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, address - Rn);
6375 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
6392 // if Rn == '1111' then SEE LDRB (literal);
6393 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
6415 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
6457 uint32_t Rn = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
6462 offset_addr = Rn + offset;
6464 offset_addr = Rn - offset;
6470 address = Rn;
6478 context.SetRegisterPlusOffset (base_reg, address - Rn);
6534 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm5:'0', 32);
6548 // if Rn == '1111' then SEE LDRH (literal);
6549 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32);
6565 // if Rn == '1111' then SEE LDRH (literal);
6572 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm8, 32);
6592 uint32_t Rn = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
6600 offset_addr = Rn + imm32;
6602 offset_addr = Rn - imm32;
6608 address = Rn;
6616 context.SetRegisterPlusOffset (base_reg, address - Rn);
6636 context.SetRegisterPlusOffset (base_reg, address - Rn);
6794 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
6811 // if Rn == '1111' then SEE LDRH (literal);
6813 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
6834 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
6876 uint64_t Rn = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
6881 offset_addr = Rn + offset;
6883 offset_addr = Rn - offset;
6889 address = Rn;
6962 // if Rn == '1111' then SEE LDRSB (literal);
6963 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32);
6981 // if Rn == '1111' then SEE LDRSB (literal);
6987 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm8, 32);
7007 // if Rn == '1111' then SEE LDRSB (literal);
7009 // t == UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm4H:imm4L, 32);
7033 uint64_t Rn = ReadCoreReg (n, &success);
7042 offset_addr = Rn + imm32;
7044 offset_addr = Rn - imm32;
7050 address = Rn;
7058 context.SetRegisterPlusOffset (base_reg, address - Rn);
7203 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
7221 // if Rn == '1111' then SEE LDRSB (literal);
7222 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
7243 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
7283 uint64_t Rn = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
7288 offset_addr = Rn + offset;
7290 offset_addr = Rn - offset;
7296 address = Rn;
7362 // if Rn == '1111' then SEE LDRSH (literal);
7364 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32);
7381 // if Rn == '1111' then SEE LDRSH (literal);
7388 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm8, 32);
7406 // if Rn == '1111' then SEE LDRSH (literal);
7408 // t == UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm4H:imm4L, 32);
7432 uint64_t Rn = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
7438 offset_addr = Rn + imm32;
7440 offset_addr = Rn - imm32;
7447 address = Rn;
7455 context.SetRegisterPlusOffset (base_reg, address - Rn);
7476 context.SetRegisterPlusOffset (base_reg, address - Rn);
7630 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
7647 // if Rn == '1111' then SEE LDRSH (literal);
7649 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
7671 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
7703 uint64_t Rn = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
7717 offset_addr = Rn + offset;
7719 offset_addr = Rn - offset;
7725 address = Rn;
8133 // n = UInt(Rn); wback = (W == '1'); increment = FALSE; wordhigher = FALSE;
8150 // n = UInt(Rn); wback = (W == '1'); increment = TRUE; wordhigher = FALSE;
8167 // n = UInt(Rn);
8191 uint64_t Rn = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
8198 address = Rn;
8200 address = Rn - 8;
8212 context.SetRegisterPlusOffset (base_reg, address - Rn);
8234 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, Rn + 8))
8240 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, Rn - 8))
8275 uint32_t Rd, Rn;
8276 uint32_t imm32; // the immediate value to be ORed to the value obtained from Rn
8283 Rn = Bits32(opcode, 19, 16);
8289 if (Rd == 13 || (Rd == 15 && !setflags) || BadReg(Rn))
8294 Rn = Bits32(opcode, 19, 16);
8307 uint32_t val1 = ReadCoreReg(Rn, &success);
8350 uint32_t Rd, Rn, Rm;
8358 Rd = Rn = Bits32(opcode, 2, 0);
8366 Rn = Bits32(opcode, 19, 16);
8373 if (Rd == 13 || (Rd == 15 && !setflags) || BadReg(Rn) || BadReg(Rm))
8378 Rn = Bits32(opcode, 19, 16);
8392 uint32_t val1 = ReadCoreReg(Rn, &success);
8442 uint32_t Rd, Rn;
8443 uint32_t imm32; // the immediate value to be ORed to the value obtained from Rn
8450 Rn = Bits32(opcode, 19, 16);
8453 // if Rn == '1111' then SEE MOV (immediate);
8454 if (Rn == 15)
8456 if (BadReg(Rd) || Rn == 13)
8461 Rn = Bits32(opcode, 19, 16);
8473 uint32_t val1 = ReadCoreReg(Rn, &success);
8516 uint32_t Rd, Rn, Rm;
8524 Rd = Rn = Bits32(opcode, 2, 0);
8532 Rn = Bits32(opcode, 19, 16);
8536 // if Rn == '1111' then SEE MOV (register);
8537 if (Rn == 15)
8539 if (BadReg(Rd) || Rn == 13 || BadReg(Rm))
8544 Rn = Bits32(opcode, 19, 16);
8557 uint32_t val1 = ReadCoreReg(Rn, &success);
8605 uint32_t Rn; // the first operand
8607 uint32_t imm32; // the immediate value to be added to the value obtained from Rn
8611 Rn = Bits32(opcode, 5, 3);
8617 Rn = Bits32(opcode, 19, 16);
8620 if (BadReg(Rd) || BadReg(Rn))
8625 Rn = Bits32(opcode, 19, 16);
8636 // Read the register value from the operand register Rn.
8637 uint32_t reg_val = ReadCoreReg(Rn, &success);
8678 uint32_t Rn; // the first operand
8686 Rn = Bits32(opcode, 19, 16);
8691 if (BadReg(Rd) || BadReg(Rn) || BadReg(Rm))
8696 Rn = Bits32(opcode, 19, 16);
8708 // Read the register value from register Rn.
8709 uint32_t val1 = ReadCoreReg(Rn, &success);
8757 uint32_t Rn; // the first operand
8759 uint32_t imm32; // the immediate value to be added to the value obtained from Rn
8763 Rn = Bits32(opcode, 19, 16);
8774 // Read the register value from the operand register Rn.
8775 uint32_t reg_val = ReadCoreReg(Rn, &success);
8817 uint32_t Rn; // the first operand
8825 Rn = Bits32(opcode, 19, 16);
8837 // Read the register value from register Rn.
8838 uint32_t val1 = ReadCoreReg(Rn, &success);
8886 uint32_t Rn; // the first operand
8888 uint32_t imm32; // the immediate value to be added to the value obtained from Rn
8892 Rn = Bits32(opcode, 19, 16);
8895 if (BadReg(Rd) || BadReg(Rn))
8900 Rn = Bits32(opcode, 19, 16);
8911 // Read the register value from the operand register Rn.
8912 uint32_t reg_val = ReadCoreReg(Rn, &success);
8954 uint32_t Rn; // the first operand
8961 Rd = Rn = Bits32(opcode, 2, 0);
8969 Rn = Bits32(opcode, 19, 16);
8973 if (BadReg(Rd) || BadReg(Rn) || BadReg(Rm))
8978 Rn = Bits32(opcode, 19, 16);
8990 // Read the register value from register Rn.
8991 uint32_t val1 = ReadCoreReg(Rn, &success);
9035 uint32_t Rn; // the first operand
9037 uint32_t imm32; // the immediate value to be subtracted from the value obtained from Rn
9041 Rn = Bits32(opcode, 5, 3);
9046 Rd = Rn = Bits32(opcode, 10, 8);
9052 Rn = Bits32(opcode, 19, 16);
9060 // if Rn == '1101' then SEE SUB (SP minus immediate);
9061 if (Rn == 13)
9065 if (Rd == 13 || (Rd == 15 && !setflags) || Rn == 15)
9070 Rn = Bits32(opcode, 19, 16);
9074 // if Rn == '1111' then SEE ADR;
9075 if (Rn == 15)
9078 // if Rn == '1101' then SEE SUB (SP minus immediate);
9079 if (Rn == 13)
9088 // Read the register value from the operand register Rn.
9089 uint32_t reg_val = ReadCoreReg(Rn, &success);
9129 uint32_t Rn; // the first operand
9131 uint32_t imm32; // the immediate value to be subtracted from the value obtained from Rn
9135 Rn = Bits32(opcode, 19, 16);
9139 // if Rn == '1111' && S == '0' then SEE ADR;
9140 if (Rn == 15 && !setflags)
9143 // if Rn == '1101' then SEE SUB (SP minus immediate);
9144 if (Rn == 13)
9154 // Read the register value from the operand register Rn.
9155 uint32_t reg_val = ReadCoreReg(Rn, &success);
9191 uint32_t Rn;
9192 uint32_t imm32; // the immediate value to be ANDed to the value obtained from Rn
9197 Rn = Bits32(opcode, 19, 16);
9199 if (BadReg(Rn))
9203 Rn = Bits32(opcode, 19, 16);
9211 uint32_t val1 = ReadCoreReg(Rn, &success);
9249 uint32_t Rn, Rm;
9256 Rn = Bits32(opcode, 19, 16);
9259 if (BadReg(Rn) || BadReg(Rm))
9263 Rn = Bits32(opcode, 19, 16);
9272 uint32_t val1 = ReadCoreReg(Rn, &success);
9316 uint32_t Rn;
9317 uint32_t imm32; // the immediate value to be ANDed to the value obtained from Rn
9322 Rn = Bits32(opcode, 19, 16);
9324 if (BadReg(Rn))
9328 Rn = Bits32(opcode, 19, 16);
9336 uint32_t val1 = ReadCoreReg(Rn, &success);
9373 uint32_t Rn, Rm;
9380 Rn = Bits32(opcode, 2, 0);
9386 Rn = Bits32(opcode, 19, 16);
9389 if (BadReg(Rn) || BadReg(Rm))
9393 Rn = Bits32(opcode, 19, 16);
9402 uint32_t val1 = ReadCoreReg(Rn, &success);
9557 // d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); s = UInt(Rs);
9593 uint32_t Rn = ReadCoreReg (n, &success);
9597 AddWithCarryResult res = AddWithCarry (Rn, shifted, 0);
9657 // d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); setflags = !InITBlock();
9671 // if Rn == ?1101? then SEE SUB (SP minus register);
9672 // d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); setflags = (S == ?1?);
9688 // if Rn == ?1101? then SEE SUB (SP minus register);
9689 // d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); setflags = (S == ?1?);
9718 uint32_t Rn = ReadCoreReg (n, &success);
9722 AddWithCarryResult res = AddWithCarry (Rn, ~shifted, 1);
9778 // d = UInt(Rd); t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm8:?00?, 32);
9795 // d = UInt(Rd); t = UInt(Rt); n = UInt(Rn); imm32 = Zeros(32); // Zero offset
9816 uint32_t Rn = ReadCoreReg (n, &success);
9820 addr_t address = Rn + imm32;
9885 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32);
9910 uint32_t Rn = ReadCoreReg (n, &success);
9916 offset_addr = Rn + imm32;
9918 offset_addr = Rn - imm32;
9925 address = Rn;
9938 context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, address - Rn);
9983 // if Rn == ?1101? && P == ?1? && U == ?0? && W == ?1? && imm12 == ?000000000100? then SEE PUSH;
9984 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32);
10005 uint32_t Rn = ReadCoreReg (n, &success);
10011 offset_addr = Rn + imm32;
10013 offset_addr = Rn - imm32;
10020 address = Rn;
10028 context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, address - Rn);
10095 //if Rn == ?1111? then SEE LDRD (literal);
10096 //t = UInt(Rt); t2 = UInt(Rt2); n = UInt(Rn); imm32 = ZeroExtend(imm8:?00?, 32);
10118 //if Rn == ?1111? then SEE LDRD (literal);
10120 //t = UInt(Rt); t2 = t+1; n = UInt(Rn); imm32 = ZeroExtend(imm4H:imm4L, 32);
10152 uint32_t Rn = ReadCoreReg (n, &success);
10158 offset_addr = Rn + imm32;
10160 Rn - imm32;
10167 address = Rn;
10175 context.SetRegisterPlusOffset (base_reg, address - Rn);
10187 context.SetRegisterPlusOffset (base_reg, (address + 4) - Rn);
10240 // t = UInt(Rt); t2 = t+1; n = UInt(Rn); m = UInt(Rm);
10274 uint32_t Rn = ReadCoreReg (n, &success);
10289 offset_addr = Rn + Rm;
10291 offset_addr = Rn - Rm;
10298 address = Rn;
10367 // t = UInt(Rt); t2 = UInt(Rt2); n = UInt(Rn); imm32 = ZeroExtend(imm8:?00?, 32);
10390 // t = UInt(Rt); t2 = t+1; n = UInt(Rn); imm32 = ZeroExtend(imm4H:imm4L, 32);
10425 uint32_t Rn = ReadCoreReg (n, &success);
10432 offset_addr = Rn + imm32;
10434 offset_addr = Rn - imm32;
10441 address = Rn;
10453 context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, address - Rn);
10462 context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, (address + 4) - Rn);
10515 // t = UInt(Rt); t2 = t+1; n = UInt(Rn); m = UInt(Rm);
10557 uint32_t Rn = ReadCoreReg (n, &success);
10568 offset_addr = Rn + Rm;
10570 offset_addr = Rn - Rm;
10577 address = Rn;
10656 // if P == ?0? && U == ?1? && W == ?1? && Rn == ?1101? then SEE VPOP;
10668 // d = UInt(D:Vd); n = UInt(Rn); imm32 = ZeroExtend(imm8:?00?, 32);
10689 // if P == ?0? && U == ?1? && W == ?1? && Rn == ?1101? then SEE VPOP;
10696 // single_regs = TRUE; add = (U == ?1?); wback = (W == ?1?); d = UInt(Vd:D); n = UInt(Rn);
10723 uint32_t Rn = ReadCoreReg (n, &success);
10730 address = Rn;
10732 address = Rn - imm32;
10741 value = Rn + imm32;
10743 value = Rn - imm32;
10746 context.SetImmediateSigned (value - Rn);
10763 context.SetRegisterPlusOffset (base_reg, address - Rn);
10777 context.SetRegisterPlusOffset (base_reg, address - Rn);
10782 context.SetRegisterPlusOffset (base_reg, (address + 4) - Rn);
10848 // if P == ?1? && U == ?0? && W == ?1? && Rn == ?1101? then SEE VPUSH;
10860 // d = UInt(D:Vd); n = UInt(Rn); imm32 = ZeroExtend(imm8:?00?, 32);
10881 // if P == ?1? && U == ?0? && W == ?1? && Rn == ?1101? then SEE VPUSH;
10888 // single_regs = TRUE; add = (U == ?1?); wback = (W == ?1?); d = UInt(Vd:D); n = UInt(Rn);
10916 uint32_t Rn = ReadCoreReg (n, &success);
10923 address = Rn;
10925 address = Rn - imm32;
10933 value = Rn + imm32;
10935 value = Rn - imm32;
10938 context.SetRegisterPlusOffset (base_reg, value - Rn);
10961 context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, address - Rn);
10981 context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, address - Rn);
10985 Rn);
10991 context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, address - Rn);
10995 context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, (address + 4) - Rn);
11045 // d = UInt(D:Vd); n = UInt(Rn);
11058 // d = UInt(Vd:D); n = UInt(Rn);
11070 uint32_t Rn = ReadCoreReg (n, &success);
11077 base = AlignPC (Rn);
11079 base = Rn;
11174 // d = UInt(D:Vd); n = UInt(Rn);
11191 // d = UInt(Vd:D); n = UInt(Rn);
11208 uint32_t Rn = ReadCoreReg (n, &success);
11215 address = Rn + imm32;
11217 address = Rn - imm32;
11226 context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, address - Rn);
11252 context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, (address + 4) - Rn);
11261 context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, (address + 4) - Rn);
11357 // d = UInt(D:Vd); n = UInt(Rn); m = UInt(Rm);
11379 uint32_t Rn = ReadCoreReg (n, &success);
11384 addr_t address = Rn;
11402 uint32_t value = Rn + offset;
11420 context.SetRegisterPlusOffset (base_reg, address - Rn);
11529 // d = UInt(D:Vd); n = UInt(Rn); m = UInt(Rm);
11551 uint32_t Rn = ReadCoreReg (n, &success);
11556 addr_t address = Rn;
11574 uint32_t value = Rn + offset;
11692 // d = UInt(D:Vd); n = UInt(Rn); m = UInt(Rm);
11718 uint32_t Rn = ReadCoreReg (n, &success);
11723 addr_t address = Rn;
11744 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, Rn + offset))
11764 context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, address - Rn);
11869 Rn); m = UInt(Rm);
11890 uint32_t Rn = ReadCoreReg (n, &success);
11895 addr_t address = Rn;
11916 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, Rn + offset))
11930 context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, address - Rn);
11991 //d = UInt(D:Vd); n = UInt(Rn); m = UInt(Rm);
12016 uint32_t Rn = ReadCoreReg (n, &success);
12021 addr_t address = Rn;
12042 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, Rn + offset))
12127 // n = UInt(Rn); imm32 = ARMExpandImm(imm12); register_form = FALSE;
12136 // n = UInt(Rn); m = UInt(Rm); register_form = TRUE;
12167 uint32_t Rn = ReadCoreReg (n, &success);
12178 result.result = Rn & operand2;
12183 result.result = Rn ^ operand2;
12188 result = AddWithCarry (Rn, ~(operand2), 1);
12193 result = AddWithCarry (~(Rn), operand2, 1);
12198 result = AddWithCarry (Rn, operand2, 0);
12203 result = AddWithCarry (Rn, operand2, APSR_C);
12208 result = AddWithCarry (Rn, ~(operand2), APSR_C);
12213 result = AddWithCarry (~(Rn), operand2, APSR_C);
12218 result.result = Rn | operand2;
12228 result.result = Rn & ~(operand2);
12286 // if Rn == '1101' && imm12 == '000000000100' then SEE PUSH;
12324 { 0x0fe00000, 0x02a00000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateADCImm, "adc{s}<c> <Rd>, <Rn>, #const"},
12326 { 0x0fe00010, 0x00a00000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateADCReg, "adc{s}<c> <Rd>, <Rn>, <Rm> {,<shift>}"},
12328 { 0x0fe00000, 0x02800000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateADDImmARM, "add{s}<c> <Rd>, <Rn>, #const"},
12330 { 0x0fe00010, 0x00800000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateADDReg, "add{s}<c> <Rd>, <Rn>, <Rm> {,<shift>}"},
12332 { 0x0fe00090, 0x00800010, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateADDRegShift, "add{s}<c> <Rd>, <Rn>, <Rm>, <type> <RS>"},
12337 { 0x0fe00000, 0x02000000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateANDImm, "and{s}<c> <Rd>, <Rn>, #const"},
12339 { 0x0fe00010, 0x00000000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateANDReg, "and{s}<c> <Rd>, <Rn>, <Rm> {,<shift>}"},
12341 { 0x0fe00000, 0x03c00000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateBICImm, "bic{s}<c> <Rd>, <Rn>, #const"},
12343 { 0x0fe00010, 0x01c00000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateBICReg, "bic{s}<c> <Rd>, <Rn>, <Rm> {,<shift>}"},
12345 { 0x0fe00000, 0x02200000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateEORImm, "eor{s}<c> <Rd>, <Rn>, #const"},
12347 { 0x0fe00010, 0x00200000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateEORReg, "eor{s}<c> <Rd>, <Rn>, <Rm> {,<shift>}"},
12349 { 0x0fe00000, 0x03800000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateORRImm, "orr{s}<c> <Rd>, <Rn>, #const"},
12351 { 0x0fe00010, 0x01800000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateORRReg, "orr{s}<c> <Rd>, <Rn>, <Rm> {,<shift>}"},
12353 { 0x0fe00000, 0x02600000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateRSBImm, "rsb{s}<c> <Rd>, <Rn>, #<const>"},
12355 { 0x0fe00010, 0x00600000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateRSBReg, "rsb{s}<c> <Rd>, <Rn>, <Rm> {,<shift>}"},
12357 { 0x0fe00000, 0x02e00000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateRSCImm, "rsc{s}<c> <Rd>, <Rn>, #<const>"},
12359 { 0x0fe00010, 0x00e00000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateRSCReg, "rsc{s}<c> <Rd>, <Rn>, <Rm> {,<shift>}"},
12361 { 0x0fe00000, 0x02c00000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSBCImm, "sbc{s}<c> <Rd>, <Rn>, #<const>"},
12363 { 0x0fe00010, 0x00c00000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSBCReg, "sbc{s}<c> <Rd>, <Rn>, <Rm> {,<shift>}"},
12365 { 0x0fe00000, 0x02400000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSUBImmARM, "sub{s}<c> <Rd>, <Rn>, #<const>"},
12369 { 0x0fe00010, 0x00400000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSUBReg, "sub{s}<c> <Rd>, <Rn>, <Rm>{,<shift>}"},
12371 { 0x0ff0f000, 0x03300000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateTEQImm, "teq<c> <Rn>, #const"},
12373 { 0x0ff0f010, 0x01300000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateTEQReg, "teq<c> <Rn>, <Rm> {,<shift>}"},
12375 { 0x0ff0f000, 0x03100000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateTSTImm, "tst<c> <Rn>, #const"},
12377 { 0x0ff0f010, 0x01100000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateTSTReg, "tst<c> <Rn>, <Rm> {,<shift>}"},
12389 { 0x0ff0f000, 0x03700000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateCMNImm, "cmn<c> <Rn>, #<const>"},
12391 { 0x0ff0f010, 0x01700000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateCMNReg, "cmn<c> <Rn>, <Rm> {,<shift>}"},
12393 { 0x0ff0f000, 0x03500000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateCMPImm, "cmp<c> <Rn>, #<const>"},
12395 { 0x0ff0f010, 0x01500000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateCMPReg, "cmp<c> <Rn>, <Rm> {,<shift>}"},
12399 { 0x0fef00f0, 0x01a00050, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateASRReg, "asr{s}<c> <Rd>, <Rn>, <Rm>"},
12403 { 0x0fef00f0, 0x01a00010, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLSLReg, "lsl{s}<c> <Rd>, <Rn>, <Rm>"},
12407 { 0x0fef00f0, 0x01a00050, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLSRReg, "lsr{s}<c> <Rd>, <Rn>, <Rm>"},
12413 { 0x0fef00f0, 0x01a00070, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateRORReg, "ror{s}<c> <Rd>, <Rn>, <Rm>"},
12418 { 0x0e10f000, 0x0210f000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSUBSPcLrEtc, "<opc>S<c> PC,#<const> | <Rn>,#<const>" },
12419 { 0x0e10f010, 0x0010f000, ARMvAll, eEncodingA2, No_VFP, eSize32, &EmulateInstructionARM::EmulateSUBSPcLrEtc, "<opc>S<c> PC,<Rn>,<Rm{,<shift>}" },
12424 { 0x0fd00000, 0x08900000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDM, "ldm<c> <Rn>{!} <registers>" },
12425 { 0x0fd00000, 0x08100000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDMDA, "ldmda<c> <Rn>{!} <registers>" },
12426 { 0x0fd00000, 0x09100000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDMDB, "ldmdb<c> <Rn>{!} <registers>" },
12427 { 0x0fd00000, 0x09900000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDMIB, "ldmib<c> <Rn<{!} <registers>" },
12428 { 0x0e500000, 0x04100000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRImmediateARM, "ldr<c> <Rt> [<Rn> {#+/-<imm12>}]" },
12429 { 0x0e500010, 0x06100000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRRegister, "ldr<c> <Rt> [<Rn> +/-<Rm> {<shift>}] {!}" },
12431 { 0xfe500010, 0x06500000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRBRegister, "ldrb<c> <Rt>, [<Rn>,+/-<Rm>{, <shift>}]{!}" },
12433 { 0x0e5000f0, 0x001000b0, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRHRegister, "ldrh<c> <Rt>,[<Rn>,+/-<Rm>]{!}" },
12434 { 0x0e5000f0, 0x005000d0, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRSBImmediate, "ldrsb<c> <Rt>, [<Rn>{,#+/-<imm8>}]" },
12436 { 0x0e5000f0, 0x001000d0, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRSBRegister, "ldrsb<c> <Rt>,[<Rn>,+/-<Rm>]{!}" },
12437 { 0x0e5000f0, 0x005000f0, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRSHImmediate, "ldrsh<c> <Rt>,[<Rn>{,#+/-<imm8>}]"},
12439 { 0x0e5000f0, 0x001000f0, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRSHRegister, "ldrsh<c> <Rt>,[<Rn>,+/-<Rm>]{!}" },
12440 { 0x0e5000f0, 0x004000d0, ARMV5TE_ABOVE, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRDImmediate, "ldrd<c> <Rt>, <Rt2>, [<Rn>,#+/-<imm8>]!"},
12441 { 0x0e500ff0, 0x000000d0, ARMV5TE_ABOVE, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRDRegister, "ldrd<c> <Rt>, <Rt2>, [<Rn>, +/-<Rm>]{!}"},
12442 { 0x0e100f00, 0x0c100b00, ARMvAll, eEncodingA1, VFPv2_ABOVE, eSize32, &EmulateInstructionARM::EmulateVLDM, "vldm{mode}<c> <Rn>{!}, <list>"},
12443 { 0x0e100f00, 0x0c100a00, ARMvAll, eEncodingA2, VFPv2v3, eSize32, &EmulateInstructionARM::EmulateVLDM, "vldm{mode}<c> <Rn>{!}, <list>"},
12444 { 0x0f300f00, 0x0d100b00, ARMvAll, eEncodingA1, VFPv2_ABOVE, eSize32, &EmulateInstructionARM::EmulateVLDR, "vldr<c> <Dd>, [<Rn>{,#+/-<imm>}]"},
12445 { 0x0f300f00, 0x0d100a00, ARMvAll, eEncodingA2, VFPv2v3, eSize32, &EmulateInstructionARM::EmulateVLDR, "vldr<c> <Sd>, [<Rn>{,#+/-<imm>}]"},
12446 { 0xffb00000, 0xf4200000, ARMvAll, eEncodingA1, AdvancedSIMD, eSize32, &EmulateInstructionARM::EmulateVLD1Multiple, "vld1<c>.<size> <list>, [<Rn>{@<align>}], <Rm>"},
12447 { 0xffb00300, 0xf4a00000, ARMvAll, eEncodingA1, AdvancedSIMD, eSize32, &EmulateInstructionARM::EmulateVLD1Single, "vld1<c>.<size> <list>, [<Rn>{@<align>}], <Rm>"},
12448 { 0xffb00f00, 0xf4a00c00, ARMvAll, eEncodingA1, AdvancedSIMD, eSize32, &EmulateInstructionARM::EmulateVLD1SingleAll, "vld1<c>.<size> <list>, [<Rn>{@<align>}], <Rm>"},
12453 { 0x0fd00000, 0x08800000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTM, "stm<c> <Rn>{!} <registers>" },
12454 { 0x0fd00000, 0x08000000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTMDA, "stmda<c> <Rn>{!} <registers>" },
12455 { 0x0fd00000, 0x09000000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTMDB, "stmdb<c> <Rn>{!} <registers>" },
12456 { 0x0fd00000, 0x09800000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTMIB, "stmib<c> <Rn>{!} <registers>" },
12457 Rn> +/-<Rm> {<shift>}]{!}" },
12458 { 0x0e5000f0, 0x000000b0, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTRHRegister, "strh<c> <Rt>,[<Rn>,+/-<Rm>[{!}" },
12459 { 0x0ff00ff0, 0x01800f90, ARMV6_ABOVE, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTREX, "strex<c> <Rd>, <Rt>, [<Rn>]"},
12460 { 0x0e500000, 0x04400000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTRBImmARM, "strb<c> <Rt>,[<Rn>,#+/-<imm12>]!"},
12461 { 0x0e500000, 0x04000000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTRImmARM, "str<c> <Rt>,[<Rn>,#+/-<imm12>]!"},
12462 { 0x0e5000f0, 0x004000f0, ARMV5TE_ABOVE, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTRDImm, "strd<c> <Rt>, <Rt2>, [<Rn> #+/-<imm8>]!"},
12463 { 0x0e500ff0, 0x000000f0, ARMV5TE_ABOVE, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTRDReg, "strd<c> <Rt>, <Rt2>, [<Rn>, +/-<Rm>]{!}"},
12464 { 0x0e100f00, 0x0c000b00, ARMvAll, eEncodingA1, VFPv2_ABOVE, eSize32, &EmulateInstructionARM::EmulateVSTM, "vstm{mode}<c> <Rn>{!} <list>"},
12465 { 0x0e100f00, 0x0c000a00, ARMvAll, eEncodingA2, VFPv2v3, eSize32, &EmulateInstructionARM::EmulateVSTM, "vstm{mode}<c> <Rn>{!} <list>"},
12466 { 0x0f300f00, 0x0d000b00, ARMvAll, eEncodingA1, VFPv2_ABOVE, eSize32, &EmulateInstructionARM::EmulateVSTR, "vstr<c> <Dd> [<Rn>{,#+/-<imm>}]"},
12467 { 0x0f300f00, 0x0d000a00, ARMvAll, eEncodingA2, VFPv2v3, eSize32, &EmulateInstructionARM::EmulateVSTR, "vstr<c> <Sd> [<Rn>{,#+/-<imm>}]"},
12468 { 0xffb00000, 0xf4000000, ARMvAll, eEncodingA1, AdvancedSIMD, eSize32, &EmulateInstructionARM::EmulateVST1Multiple, "vst1<c>.<size> <list>, [<Rn>{@<align>}], <Rm>"},
12469 { 0xffb00300, 0xf4800000, ARMvAll, eEncodingA1, AdvancedSIMD, eSize32, &EmulateInstructionARM::EmulateVST1Single, "vst1<c>.<size> <list>, [<Rn>{@<align>}], <Rm>"},
12478 { 0xfe500000, 0xf8100000, ARMV6_ABOVE, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateRFE, "rfe{<amode>} <Rn>{!}" }
12576 { 0xfffff500, 0x0000b100, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateCB, "cb{n}z <Rn>, <label>"},
12578 { 0xfff0fff0, 0xe8d0f000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateTB, "tbb<c> <Rn>, <Rm>"},
12580 { 0xfff0fff0, 0xe8d0f010, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateTB, "tbh<c> <Rn>, <Rm>, lsl #1"},
12586 { 0xfbe08000, 0xf1400000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateADCImm, "adc{s}<c> <Rd>, <Rn>, #<const>"},
12589 { 0xffe08000, 0xeb400000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateADCReg, "adc{s}<c>.w <Rd>, <Rn>, <Rm> {,<shift>}"},
12591 { 0xfffffe00, 0x00001800, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateADDReg, "adds|add<c> <Rd>, <Rn>, <Rm>"},
12599 { 0xfbe08000, 0xf0000000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateANDImm, "and{s}<c> <Rd>, <Rn>, #<const>"},
12602 { 0xffe08000, 0xea000000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateANDReg, "and{s}<c>.w <Rd>, <Rn>, <Rm> {,<shift>}"},
12604 { 0xfbe08000, 0xf0200000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateBICImm, "bic{s}<c> <Rd>, <Rn>, #<const>"},
12607 { 0xffe08000, 0xea200000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateBICReg, "bic{s}<c>.w <Rd>, <Rn>, <Rm> {,<shift>}"},
12609 { 0xfbe08000, 0xf0800000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateEORImm, "eor{s}<c> <Rd>, <Rn>, #<const>"},
12612 { 0xffe08000, 0xea800000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateEORReg, "eor{s}<c>.w <Rd>, <Rn>, <Rm> {,<shift>}"},
12614 { 0xfbe08000, 0xf0400000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateORRImm, "orr{s}<c> <Rd>, <Rn>, #<const>"},
12617 { 0xffe08000, 0xea400000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateORRReg, "orr{s}<c>.w <Rd>, <Rn>, <Rm> {,<shift>}"},
12619 { 0xffffffc0, 0x00004240, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateRSBImm, "rsbs|rsb<c> <Rd>, <Rn>, #0"},
12620 { 0xfbe08000, 0xf1c00000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateRSBImm, "rsb{s}<c>.w <Rd>, <Rn>, #<const>"},
12622 { 0xffe08000, 0xea400000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateRSBReg, "rsb{s}<c>.w <Rd>, <Rn>, <Rm> {,<shift>}"},
12624 { 0xfbe08000, 0xf1600000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSBCImm, "sbc{s}<c> <Rd>, <Rn>, #<const>"},
12627 { 0xffe08000, 0xeb600000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateSBCReg, "sbc{s}<c>.w <Rd>, <Rn>, <Rm> {,<shift>}"},
12629 { 0xfffffe00, 0x00001c00, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateADDImmThumb, "adds|add<c> <Rd>,<Rn>,#<imm3>" },
12631 { 0xfbe08000, 0xf1000000, ARMV6T2_ABOVE, eEncodingT3, No_VFP, eSize32, &EmulateInstructionARM::EmulateADDImmThumb, "add{s}<c>.w <Rd>,<Rn>,#<const>" },
12632 { 0xfbf08000, 0xf2000000, ARMV6T2_ABOVE, eEncodingT4, No_VFP, eSize32, &EmulateInstructionARM::EmulateADDImmThumb, "addw<c> <Rd>,<Rn>,#<imm12>" },
12634 Rn> #imm3"},
12636 { 0xfbe08000, 0xf1a00000, ARMV6T2_ABOVE, eEncodingT3, No_VFP, eSize32, &EmulateInstructionARM::EmulateSUBImmThumb, "sub{s}<c>.w <Rd>, <Rn>, #<const>"},
12637 { 0xfbf08000, 0xf2a00000, ARMV6T2_ABOVE, eEncodingT4, No_VFP, eSize32, &EmulateInstructionARM::EmulateSUBImmThumb, "subw<c> <Rd>, <Rn>, #imm12"},
12642 { 0xfffffe00, 0x00001a00, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateSUBReg, "subs|sub<c> <Rd>, <Rn>, <Rm>"},
12643 { 0xffe08000, 0xeba00000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateSUBReg, "sub{s}<c>.w <Rd>, <Rn>, <Rm>{,<shift>}"},
12645 { 0xfbf08f00, 0xf0900f00, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateTEQImm, "teq<c> <Rn>, #<const>"},
12647 { 0xfff08f00, 0xea900f00, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateTEQReg, "teq<c> <Rn>, <Rm> {,<shift>}"},
12649 { 0xfbf08f00, 0xf0100f00, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateTSTImm, "tst<c> <Rn>, #<const>"},
12652 { 0xfff08f00, 0xea100f00, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateTSTReg, "tst<c>.w <Rn>, <Rm> {,<shift>}"},
12671 { 0xfbf08f00, 0xf1100f00, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateCMNImm, "cmn<c> <Rn>, #<const>"},
12673 { 0xffffffc0, 0x000042c0, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateCMNReg, "cmn<c> <Rn>, <Rm>"},
12674 { 0xfff08f00, 0xeb100f00, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateCMNReg, "cmn<c> <Rn>, <Rm> {,<shift>}"},
12676 { 0xfffff800, 0x00002800, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateCMPImm, "cmp<c> <Rn>, #imm8"},
12677 { 0xfbf08f00, 0xf1b00f00, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateCMPImm, "cmp<c>.w <Rn>, #<const>"},
12678 // cmp (register) (Rn and Rm both from r0-r7)
12679 { 0xffffffc0, 0x00004280, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateCMPReg, "cmp<c> <Rn>, <Rm>"},
12680 // cmp (register) (Rn and Rm not both from r0-r7)
12681 { 0xffffff00, 0x00004500, ARMvAll, eEncodingT2, No_VFP, eSize16, &EmulateInstructionARM::EmulateCMPReg, "cmp<c> <Rn>, <Rm>"},
12687 { 0xffe0f0f0, 0xfa40f000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateASRReg, "asr{s}<c>.w <Rd>, <Rn>, <Rm>"},
12693 { 0xffe0f0f0, 0xfa00f000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateLSLReg, "lsl{s}<c>.w <Rd>, <Rn>, <Rm>"},
12699 { 0xffe0f0f0, 0xfa20f000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateLSRReg, "lsr{s}<c>.w <Rd>, <Rn>, <Rm>"},
12706 { 0xffe0f0f0, 0xfa60f000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateRORReg, "ror{s}<c>.w <Rd>, <Rn>, <Rm>"},
12708 { 0xffffffc0, 0x00004340, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateMUL, "muls <Rdm>,<Rn>,<Rdm>" },
12710 { 0xfff0f0f0, 0xfb00f000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateMUL, "mul<c> <Rd>,<Rn>,<Rm>" },
12720 { 0xffd0ffff, 0xe810c000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateRFE, "rfedb<c> <Rn>{!}" },
12721 { 0xffd0ffff, 0xe990c000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateRFE, "rfe{ia}<c> <Rn>{!}" },
12726 { 0xfffff800, 0x0000c800, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateLDM, "ldm<c> <Rn>{!} <registers>" },
12727 { 0xffd02000, 0xe8900000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDM, "ldm<c>.w <Rn>{!} <registers>" },
12728 { 0xffd00000, 0xe9100000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDMDB, "ldmdb<c> <Rn>{!} <registers>" },
12729 { 0xfffff800, 0x00006800, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateLDRRtRnImm, "ldr<c> <Rt>, [<Rn>{,#imm}]"},
12731 { 0xfff00000, 0xf8d00000, ARMV6T2_ABOVE, eEncodingT3, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRRtRnImm, "ldr<c>.w <Rt>, [<Rn>{,#imm12}]"},
12732 { 0xfff00800, 0xf8500800, ARMV6T2_ABOVE, eEncodingT4, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRRtRnImm, "ldr<c> <Rt>, [<Rn>{,#+/-<imm8>}]{!}"},
12735 { 0xfffffe00, 0x00005800, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateLDRRegister, "ldr<c> <Rt>, [<Rn>, <Rm>]" },
12736 { 0xfff00fc0, 0xf8500000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRRegister, "ldr<c>.w <Rt>, [<Rn>,<Rm>{,LSL #<imm2>}]" },
12737 { 0xfffff800, 0x00007800, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateLDRBImmediate, "ldrb<c> <Rt>,[<Rn>{,#<imm5>}]" },
12738 { 0xfff00000, 0xf8900000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRBImmediate, "ldrb<c>.w <Rt>,[<Rn>{,#<imm12>}]" },
12739 { 0xfff00800, 0xf8100800, ARMV6T2_ABOVE, eEncodingT3, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRBImmediate, "ldrb<c> <Rt>,[<Rn>, #+/-<imm8>]{!}" },
12741 { 0xfffffe00, 0x00005c00, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateLDRBRegister, "ldrb<c> <Rt>,[<Rn>,<Rm>]" },
12742 { 0xfff00fc0, 0xf8100000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRBRegister, "ldrb<c>.w <Rt>,[<Rn>,<Rm>{,LSL #imm2>}]" },
12743 { 0xfffff800, 0x00008800, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateLDRHImmediate, "ldrh<c> <Rt>, [<Rn>{,#<imm>}]" },
12744 { 0xfff00000, 0xf8b00000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRHImmediate, "ldrh<c>.w <Rt>,[<Rn>{,#<imm12>}]" },
12745 { 0xfff00800, 0xf8300800, ARMV6T2_ABOVE, eEncodingT3, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRHImmediate, "ldrh<c> <Rt>,[<Rn>,#+/-<imm8>]{!}" },
12747 { 0xfffffe00, 0x00005a00, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateLDRHRegister, "ldrh<c> <Rt>, [<Rn>,<Rm>]" },
12748 { 0xfff00fc0, 0xf8300000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRHRegister, "ldrh<c>.w <Rt>,[<Rn>,<Rm>{,LSL #<imm2>}]" },
12749 { 0xfff00000, 0xf9900000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRSBImmediate, "ldrsb<c> <Rt>,[<Rn>,#<imm12>]" },
12750 { 0xfff00800, 0xf9100800, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRSBImmediate, "ldrsb<c> <Rt>,[<Rn>,#+/-<imm8>]" },
12752 { 0xfffffe00, 0x00005600, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateLDRSBRegister, "ldrsb<c> <Rt>,[<Rn>,<Rm>]" },
12753 { 0xfff00fc0, 0xf9100000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRSBRegister, "ldrsb<c>.w <Rt>,[<Rn>,<Rm>{,LSL #imm2>}]" },
12754 { 0xfff00000, 0xf9b00000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRSHImmediate, "ldrsh<c> <Rt>,[<Rn>,#<imm12>]" },
12755 { 0xfff00800, 0xf9300800, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRSHImmediate, "ldrsh<c> <Rt>,[<Rn>,#+/-<imm8>]" },
12757 { 0xfffffe00, 0x00005e00, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateLDRSHRegister, "ldrsh<c> <Rt>,[<Rn>,<Rm>]" },
12758 { 0xfff00fc0, 0xf9300000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRSHRegister, "ldrsh<c>.w <Rt>,[<Rn>,<Rm>{,LSL #<imm2>}]" },
12759 { 0xfe500000, 0xe8500000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRDImmediate, "ldrd<c> <Rt>, <Rt2>, [<Rn>,#+/-<imm>]!"},
12760 { 0xfe100f00, 0xec100b00, ARMvAll, eEncodingT1, VFPv2_ABOVE, eSize32, &EmulateInstructionARM::EmulateVLDM, "vldm{mode}<c> <Rn>{!}, <list>"},
12761 { 0xfe100f00, 0xec100a00, ARMvAll, eEncodingT2, VFPv2v3, eSize32, &EmulateInstructionARM::EmulateVLDM, "vldm{mode}<c> <Rn>{!}, <list>" },
12762 { 0xffe00f00, 0xed100b00, ARMvAll, eEncodingT1, VFPv2_ABOVE, eSize32, &EmulateInstructionARM::EmulateVLDR, "vldr<c> <Dd>, [<Rn>{,#+/-<imm>}]"},
12763 { 0xff300f00, 0xed100a00, ARMvAll, eEncodingT2, VFPv2v3, eSize32, &EmulateInstructionARM::EmulateVLDR, "vldr<c> <Sd>, {<Rn>{,#+/-<imm>}]"},
12764 { 0xffb00000, 0xf9200000, ARMvAll, eEncodingT1, AdvancedSIMD, eSize32, &EmulateInstructionARM::EmulateVLD1Multiple, "vld1<c>.<size> <list>, [<Rn>{@<align>}],<Rm>"},
12765 { 0xffb00300, 0xf9a00000, ARMvAll, eEncodingT1, AdvancedSIMD, eSize32, &EmulateInstructionARM::EmulateVLD1Single, "vld1<c>.<size> <list>, [<Rn>{@<align>}],<Rm>"},
12766 { 0xffb00f00, 0xf9a00c00, ARMvAll, eEncodingT1, AdvancedSIMD, eSize32, &EmulateInstructionARM::EmulateVLD1SingleAll, "vld1<c>.<size> <list>, [<Rn>{@<align>}], <Rm>"},
12771 { 0xfffff800, 0x0000c000, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateSTM, "stm<c> <Rn>{!} <registers>" },
12772 { 0xffd00000, 0xe8800000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTM, "stm<c>.w <Rn>{!} <registers>" },
12773 { 0xffd00000, 0xe9000000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTMDB, "stmdb<c> <Rn>{!} <registers>" },
12774 { 0xfffff800, 0x00006000, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateSTRThumb, "str<c> <Rt>, [<Rn>{,#<imm>}]" },
12776 { 0xfff00000, 0xf8c00000, ARMV6T2_ABOVE, eEncodingT3, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTRThumb, "str<c>.w <Rt>, [<Rn>,#<imm12>]" },
12777 Rn>,#+/-<imm8>]" },
12778 { 0xfffffe00, 0x00005000, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateSTRRegister, "str<c> <Rt> ,{<Rn>, <Rm>]" },
12779 { 0xfff00fc0, 0xf8400000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTRRegister, "str<c>.w <Rt>, [<Rn>, <Rm> {lsl #imm2>}]" },
12780 { 0xfffff800, 0x00007000, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateSTRBThumb, "strb<c> <Rt>, [<Rn>, #<imm5>]" },
12781 { 0xfff00000, 0xf8800000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTRBThumb, "strb<c>.w <Rt>, [<Rn>, #<imm12>]" },
12782 { 0xfff00800, 0xf8000800, ARMV6T2_ABOVE, eEncodingT3, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTRBThumb, "strb<c> <Rt> ,[<Rn>, #+/-<imm8>]{!}" },
12783 { 0xfffffe00, 0x00005200, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateSTRHRegister, "strh<c> <Rt>,[<Rn>,<Rm>]" },
12784 { 0xfff00fc0, 0xf8200000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTRHRegister, "strh<c>.w <Rt>,[<Rn>,<Rm>{,LSL #<imm2>}]" },
12785 { 0xfff00000, 0xe8400000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTREX, "strex<c> <Rd>, <Rt>, [<Rn{,#<imm>}]" },
12786 { 0xfe500000, 0xe8400000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTRDImm, "strd<c> <Rt>, <Rt2>, [<Rn>, #+/-<imm>]!"},
12787 { 0xfe100f00, 0xec000b00, ARMvAll, eEncodingT1, VFPv2_ABOVE, eSize32, &EmulateInstructionARM::EmulateVSTM, "vstm{mode}<c> <Rn>{!}, <list>"},
12788 { 0xfea00f00, 0xec000a00, ARMvAll, eEncodingT2, VFPv2v3, eSize32, &EmulateInstructionARM::EmulateVSTM, "vstm{mode}<c> <Rn>{!}, <list>"},
12789 { 0xff300f00, 0xed000b00, ARMvAll, eEncodingT1, VFPv2_ABOVE, eSize32, &EmulateInstructionARM::EmulateVSTR, "vstr<c> <Dd>, [<Rn>{,#+/-<imm>}]"},
12790 { 0xff300f00, 0xed000a00, ARMvAll, eEncodingT2, VFPv2v3, eSize32, &EmulateInstructionARM::EmulateVSTR, "vstr<c> <Sd>, [<Rn>{,#+/-<imm>}]"},
12791 { 0xffb00000, 0xf9000000, ARMvAll, eEncodingT1, AdvancedSIMD, eSize32, &EmulateInstructionARM::EmulateVST1Multiple, "vst1<c>.<size> <list>, [<Rn>{@<align>}], <Rm>"},
12792 { 0xffb00300, 0xf9800000, ARMvAll, eEncodingT1, AdvancedSIMD, eSize32, &EmulateInstructionARM::EmulateVST1Single, "vst1<c>.<size> <list>, [<Rn>{@<align>}], <Rm>"},
