Lines Matching defs:Rt
367 uint32_t Rt; // the source register
386 Rt = Bits32(opcode, 15, 12);
388 if (BadReg(Rt))
390 registers = (1u << Rt);
399 Rt = Bits32(opcode, 15, 12);
401 if (Rt == dwarf_sp)
403 registers = (1u << Rt);
490 uint32_t Rt; // the destination register
512 Rt = Bits32(opcode, 15, 12);
514 if (Rt == 13)
516 if (Rt == 15 && InITBlock() && !LastInITBlock())
518 registers = (1u << Rt);
531 Rt = Bits32(opcode, 15, 12);
533 if (Rt == dwarf_sp)
535 registers = (1u << Rt);
1218 uint32_t Rt; // the destination register
1226 Rt = Bits32(opcode, 10, 8);
1231 Rt = Bits32(opcode, 15, 12);
1234 if (Rt == 15 && InITBlock() && !LastInITBlock())
1252 if (Rt == 15)
1265 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + Rt, data))
1904 uint32_t Rt; // the source register
1913 Rt = Bits32(opcode, 15, 12);
1924 if (wback && ((Rn == 15) || (Rn == Rt)))
1951 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + Rt, dwarf_reg);
1953 if (Rt != 15)
1955 uint32_t reg_value = ReadCoreReg(Rt, &success);
3877 uint32_t Rt; // the destination register
3886 Rt = Bits32(opcode, 2, 0);
3897 // t = UInt(Rt); n = 13; imm32 = ZeroExtend(imm8:'00', 32);
3898 Rt = Bits32 (opcode, 10, 8);
3911 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32);
3912 Rt = Bits32 (opcode, 15, 12);
3922 if ((Rt == 15) && InITBlock() && !LastInITBlock())
3935 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm8, 32);
3936 Rt = Bits32 (opcode, 15, 12);
3946 if ((wback && (Rn == Rt)) || ((Rt == 15) && InITBlock() && !LastInITBlock()))
3976 // Prepare to write to the Rt register.
3986 if (Rt == 15)
3998 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + Rt, data))
4002 WriteBits32Unknown (Rt);
4596 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm5:'00', 32);
4608 // t = UInt(Rt); n = 13; imm32 = ZeroExtend(imm8:'00', 32);
4624 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32);
4647 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm8, 32);
4765 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
4785 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
4807 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
4942 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm5, 32);
4958 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32);
4979 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm8, 32);
5086 Rt); n = UInt(Rn); m = UInt(Rm);
5104 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
5128 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
5194 uint32_t Rt = ReadCoreReg (t, &success);
5208 if (!MemUWrite (context, address, Bits32 (Rt, 15, 0), 2))
5815 // t == UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32);
5958 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
5976 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
6003 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
6156 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm5, 32);
6169 // if Rt == '1111' then SEE PLD;
6171 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32);
6188 // if Rt == '1111' && P == '1' && U == '0' && W == '0' then SEE PLD;
6195 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm8, 32);
6286 // if Rt == '1111' then SEE PLD;
6287 // t = UInt(Rt); imm32 = ZeroExtend(imm12, 32); add = (U == '1');
6299 // t == UInt(Rt); imm32 = ZeroExtend(imm12, 32); add = (U == '1');
6375 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
6391 // if Rt == '1111' then SEE PLD;
6393 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
6415 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
6534 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm5:'0', 32);
6547 // if Rt == '1111' then SEE "Unallocated memory hints";
6549 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32);
6566 // if Rt == '1111' && P == '1' && U == '0' && W == '0' then SEE "Unallocated memory hints";
6572 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm8, 32);
6678 // if Rt == '1111' then SEE "Unallocated memory hints";
6679 // t = UInt(Rt); imm32 = ZeroExtend(imm12, 32); add = (U == '1');
6695 // t == UInt(Rt); imm32 = ZeroExtend(imm4H:imm4L, 32); add = (U == '1');
6794 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
6812 // if Rt == '1111' then SEE "Unallocated memory hints";
6813 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
6834 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
6961 // if Rt == '1111' then SEE PLI;
6963 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32);
6980 // if Rt == '1111' && P == '1' && U == '0' && W == '0' then SEE PLI;
6987 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm8, 32);
7009 // t == UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm4H:imm4L, 32);
7106 // if Rt == '1111' then SEE PLI;
7107 // t = UInt(Rt); imm32 = ZeroExtend(imm12, 32); add = (U == '1');
7120 // t == UInt(Rt); imm32 = ZeroExtend(imm4H:imm4L, 32); add = (U == '1');
7203 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
7220 // if Rt == '1111' then SEE PLI;
7222 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
7243 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
7363 // if Rt == '1111' then SEE "Unallocated memory hints";
7364 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32);
7382 // if Rt == '1111' && P == '1' && U == '0' && W == '0' then SEE "Unallocated memory hints";
7388 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm8, 32);
7408 // t == UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm4H:imm4L, 32);
7518 // if Rt == '1111' then SEE "Unallocated memory hints";
7519 // t = UInt(Rt); imm32 = ZeroExtend(imm12, 32); add = (U == '1');
7532 // t == UInt(Rt); imm32 = ZeroExtend(imm4H:imm4L, 32); add = (U == '1');
7630 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
7648 // if Rt == '1111' then SEE "Unallocated memory hints";
7649 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
7671 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
9778 // d = UInt(Rd); t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm8:?00?, 32);
9795 // d = UInt(Rd); t = UInt(Rt); n = UInt(Rn); imm32 = Zeros(32); // Zero offset
9836 uint32_t Rt = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + t, 0, &success);
9840 if (!MemAWrite (context, address, Rt, addr_byte_size))
9885 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32);
9928 uint32_t Rt = ReadCoreReg (t, &success);
9940 if (!MemUWrite (context, address, Bits32 (Rt, 7, 0), 1))
9984 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32);
10031 uint32_t Rt = ReadCoreReg (t, &success);
10046 if (!MemUWrite (context, address, Rt, addr_byte_size))
10096 //t = UInt(Rt); t2 = UInt(Rt2); n = UInt(Rn); imm32 = ZeroExtend(imm8:?00?, 32);
10119 //if Rt<0> == ?1? then UNPREDICTABLE;
10120 //t = UInt(Rt); t2 = t+1; n = UInt(Rn); imm32 = ZeroExtend(imm4H:imm4L, 32);
10239 // if Rt<0> == ?1? then UNPREDICTABLE;
10240 // t = UInt(Rt); t2 = t+1; n = UInt(Rn); m = UInt(Rm);
10367 // t = UInt(Rt); t2 = UInt(Rt2); n = UInt(Rn); imm32 = ZeroExtend(imm8:?00?, 32);
10389 // if Rt<0> == ?1? then UNPREDICTABLE;
10390 // t = UInt(Rt); t2 = t+1; n = UInt(Rn); imm32 = ZeroExtend(imm4H:imm4L, 32);
10514 // if Rt<0> == ?1? then UNPREDICTABLE;
10515 // t = UInt(Rt); t2 = t+1; n = UInt(Rn); m = UInt(Rm);
10579 uint32_t Rt = ReadCoreReg (t, &success);
10590 if (!MemAWrite (context, address, Rt, addr_byte_size))
12287 { 0x0e5f0000, 0x040d0000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTRRtSP, "str Rt, [sp, #-imm12]!" },
12428 { 0x0e500000, 0x04100000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRImmediateARM, "ldr<c> <Rt> [<Rn> {#+/-<imm12>}]" },
12429 { 0x0e500010, 0x06100000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRRegister, "ldr<c> <Rt> [<Rn> +/-<Rm> {<shift>}] {!}" },
12430 { 0x0e5f0000, 0x045f0000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRBLiteral, "ldrb<c> <Rt>, [...]"},
12431 { 0xfe500010, 0x06500000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRBRegister, "ldrb<c> <Rt>, [<Rn>,+/-<Rm>{, <shift>}]{!}" },
12432 { 0x0e5f00f0, 0x005f00b0, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRHLiteral, "ldrh<c> <Rt>, <label>" },
12433 { 0x0e5000f0, 0x001000b0, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRHRegister, "ldrh<c> <Rt>,[<Rn>,+/-<Rm>]{!}" },
12434 { 0x0e5000f0, 0x005000d0, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRSBImmediate, "ldrsb<c> <Rt>, [<Rn>{,#+/-<imm8>}]" },
12435 { 0x0e5f00f0, 0x005f00d0, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRSBLiteral, "ldrsb<c> <Rt> <label>" },
12436 { 0x0e5000f0, 0x001000d0, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRSBRegister, "ldrsb<c> <Rt>,[<Rn>,+/-<Rm>]{!}" },
12437 { 0x0e5000f0, 0x005000f0, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRSHImmediate, "ldrsh<c> <Rt>,[<Rn>{,#+/-<imm8>}]"},
12438 { 0x0e5f00f0, 0x005f00f0, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRSHLiteral, "ldrsh<c> <Rt>,<label>" },
12439 { 0x0e5000f0, 0x001000f0, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRSHRegister, "ldrsh<c> <Rt>,[<Rn>,+/-<Rm>]{!}" },
12440 { 0x0e5000f0, 0x004000d0, ARMV5TE_ABOVE, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRDImmediate, "ldrd<c> <Rt>, <Rt2>, [<Rn>,#+/-<imm8>]!"},
12441 { 0x0e500ff0, 0x000000d0, ARMV5TE_ABOVE, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRDRegister, "ldrd<c> <Rt>, <Rt2>, [<Rn>, +/-<Rm>]{!}"},
12457 Rt> [<Rn> +/-<Rm> {<shift>}]{!}" },
12458 { 0x0e5000f0, 0x000000b0, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTRHRegister, "strh<c> <Rt>,[<Rn>,+/-<Rm>[{!}" },
12459 { 0x0ff00ff0, 0x01800f90, ARMV6_ABOVE, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTREX, "strex<c> <Rd>, <Rt>, [<Rn>]"},
12460 { 0x0e500000, 0x04400000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTRBImmARM, "strb<c> <Rt>,[<Rn>,#+/-<imm12>]!"},
12461 { 0x0e500000, 0x04000000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTRImmARM, "str<c> <Rt>,[<Rn>,#+/-<imm12>]!"},
12462 { 0x0e5000f0, 0x004000f0, ARMV5TE_ABOVE, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTRDImm, "strd<c> <Rt>, <Rt2>, [<Rn> #+/-<imm8>]!"},
12463 { 0x0e500ff0, 0x000000f0, ARMV5TE_ABOVE, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTRDReg, "strd<c> <Rt>, <Rt2>, [<Rn>, +/-<Rm>]{!}"},
12517 { 0xfffff800, 0x00004800, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateLDRRtPCRelative, "ldr <Rt>, [PC, #imm]"},
12729 { 0xfffff800, 0x00006800, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateLDRRtRnImm, "ldr<c> <Rt>, [<Rn>{,#imm}]"},
12730 { 0xfffff800, 0x00009800, ARMV4T_ABOVE, eEncodingT2, No_VFP, eSize16, &EmulateInstructionARM::EmulateLDRRtRnImm, "ldr<c> <Rt>, [SP{,#imm}]"},
12731 { 0xfff00000, 0xf8d00000, ARMV6T2_ABOVE, eEncodingT3, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRRtRnImm, "ldr<c>.w <Rt>, [<Rn>{,#imm12}]"},
12732 { 0xfff00800, 0xf8500800, ARMV6T2_ABOVE, eEncodingT4, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRRtRnImm, "ldr<c> <Rt>, [<Rn>{,#+/-<imm8>}]{!}"},
12734 { 0xff7f0000, 0xf85f0000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRRtPCRelative, "ldr<c>.w <Rt>, [PC, +/-#imm}]"},
12735 { 0xfffffe00, 0x00005800, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateLDRRegister, "ldr<c> <Rt>, [<Rn>, <Rm>]" },
12736 { 0xfff00fc0, 0xf8500000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRRegister, "ldr<c>.w <Rt>, [<Rn>,<Rm>{,LSL #<imm2>}]" },
12737 { 0xfffff800, 0x00007800, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateLDRBImmediate, "ldrb<c> <Rt>,[<Rn>{,#<imm5>}]" },
12738 { 0xfff00000, 0xf8900000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRBImmediate, "ldrb<c>.w <Rt>,[<Rn>{,#<imm12>}]" },
12739 { 0xfff00800, 0xf8100800, ARMV6T2_ABOVE, eEncodingT3, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRBImmediate, "ldrb<c> <Rt>,[<Rn>, #+/-<imm8>]{!}" },
12740 { 0xff7f0000, 0xf81f0000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRBLiteral, "ldrb<c> <Rt>,[...]" },
12741 { 0xfffffe00, 0x00005c00, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateLDRBRegister, "ldrb<c> <Rt>,[<Rn>,<Rm>]" },
12742 { 0xfff00fc0, 0xf8100000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRBRegister, "ldrb<c>.w <Rt>,[<Rn>,<Rm>{,LSL #imm2>}]" },
12743 { 0xfffff800, 0x00008800, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateLDRHImmediate, "ldrh<c> <Rt>, [<Rn>{,#<imm>}]" },
12744 { 0xfff00000, 0xf8b00000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRHImmediate, "ldrh<c>.w <Rt>,[<Rn>{,#<imm12>}]" },
12745 { 0xfff00800, 0xf8300800, ARMV6T2_ABOVE, eEncodingT3, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRHImmediate, "ldrh<c> <Rt>,[<Rn>,#+/-<imm8>]{!}" },
12746 { 0xff7f0000, 0xf83f0000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRHLiteral, "ldrh<c> <Rt>, <label>" },
12747 { 0xfffffe00, 0x00005a00, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateLDRHRegister, "ldrh<c> <Rt>, [<Rn>,<Rm>]" },
12748 { 0xfff00fc0, 0xf8300000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRHRegister, "ldrh<c>.w <Rt>,[<Rn>,<Rm>{,LSL #<imm2>}]" },
12749 { 0xfff00000, 0xf9900000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRSBImmediate, "ldrsb<c> <Rt>,[<Rn>,#<imm12>]" },
12750 { 0xfff00800, 0xf9100800, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRSBImmediate, "ldrsb<c> <Rt>,[<Rn>,#+/-<imm8>]" },
12751 { 0xff7f0000, 0xf91f0000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRSBLiteral, "ldrsb<c> <Rt>, <label>" },
12752 { 0xfffffe00, 0x00005600, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateLDRSBRegister, "ldrsb<c> <Rt>,[<Rn>,<Rm>]" },
12753 { 0xfff00fc0, 0xf9100000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRSBRegister, "ldrsb<c>.w <Rt>,[<Rn>,<Rm>{,LSL #imm2>}]" },
12754 { 0xfff00000, 0xf9b00000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRSHImmediate, "ldrsh<c> <Rt>,[<Rn>,#<imm12>]" },
12755 { 0xfff00800, 0xf9300800, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRSHImmediate, "ldrsh<c> <Rt>,[<Rn>,#+/-<imm8>]" },
12756 { 0xff7f0000, 0xf93f0000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRSHLiteral, "ldrsh<c> <Rt>,<label>" },
12757 { 0xfffffe00, 0x00005e00, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateLDRSHRegister, "ldrsh<c> <Rt>,[<Rn>,<Rm>]" },
12758 { 0xfff00fc0, 0xf9300000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRSHRegister, "ldrsh<c>.w <Rt>,[<Rn>,<Rm>{,LSL #<imm2>}]" },
12759 { 0xfe500000, 0xe8500000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRDImmediate, "ldrd<c> <Rt>, <Rt2>, [<Rn>,#+/-<imm>]!"},
12774 { 0xfffff800, 0x00006000, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateSTRThumb, "str<c> <Rt>, [<Rn>{,#<imm>}]" },
12775 { 0xfffff800, 0x00009000, ARMV4T_ABOVE, eEncodingT2, No_VFP, eSize16, &EmulateInstructionARM::EmulateSTRThumb, "str<c> <Rt>, [SP,#<imm>]" },
12776 { 0xfff00000, 0xf8c00000, ARMV6T2_ABOVE, eEncodingT3, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTRThumb, "str<c>.w <Rt>, [<Rn>,#<imm12>]" },
12777 Rt>, [<Rn>,#+/-<imm8>]" },
12778 { 0xfffffe00, 0x00005000, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateSTRRegister, "str<c> <Rt> ,{<Rn>, <Rm>]" },
12779 { 0xfff00fc0, 0xf8400000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTRRegister, "str<c>.w <Rt>, [<Rn>, <Rm> {lsl #imm2>}]" },
12780 { 0xfffff800, 0x00007000, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateSTRBThumb, "strb<c> <Rt>, [<Rn>, #<imm5>]" },
12781 { 0xfff00000, 0xf8800000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTRBThumb, "strb<c>.w <Rt>, [<Rn>, #<imm12>]" },
12782 { 0xfff00800, 0xf8000800, ARMV6T2_ABOVE, eEncodingT3, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTRBThumb, "strb<c> <Rt> ,[<Rn>, #+/-<imm8>]{!}" },
12783 { 0xfffffe00, 0x00005200, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateSTRHRegister, "strh<c> <Rt>,[<Rn>,<Rm>]" },
12784 { 0xfff00fc0, 0xf8200000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTRHRegister, "strh<c>.w <Rt>,[<Rn>,<Rm>{,LSL #<imm2>}]" },
12785 { 0xfff00000, 0xe8400000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTREX, "strex<c> <Rd>, <Rt>, [<Rn{,#<imm>}]" },
12786 { 0xfe500000, 0xe8400000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTRDImm, "strd<c> <Rt>, <Rt2>, [<Rn>, #+/-<imm>]!"},
