Lines Matching defs:imm12
627 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
865 // d = UInt(Rd); setflags = (S == ?1?); (imm32, carry) = ARMExpandImm_C(imm12, APSR.C);
878 // d = UInt(Rd); setflags = FALSE; imm32 = ZeroExtend(imm4:imm12, 32);
882 uint32_t imm12 = Bits32 (opcode, 11, 0);
883 imm32 = (imm4 << 12) | imm12;
1232 imm32 = Bits32(opcode, 11, 0) << 2; // imm32 = ZeroExtend(imm12, 32);
1717 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
1769 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
1849 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
1905 uint32_t imm12;
1914 imm12 = Bits32(opcode, 11, 0);
1932 offset_addr = sp + imm12;
1934 offset_addr = sp - imm12;
2591 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
2736 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
2860 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
3911 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32);
4624 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32);
4958 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32);
5272 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
5427 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
5497 imm32 = ARMExpandImm_C(opcode, APSR_C, carry); // (imm32, carry) = ARMExpandImm(imm12, APSR.C)
5659 imm32 = ARMExpandImm_C(opcode, APSR_C, carry); // (imm32, carry) = ARMExpandImm(imm12, APSR.C)
5814 // if Rn == '1101' && P == '0' && U == '1' && W == '0' && imm12 == '000000000100' then SEE POP;
5815 // t == UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32);
6171 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32);
6287 // t = UInt(Rt); imm32 = ZeroExtend(imm12, 32); add = (U == '1');
6299 // t == UInt(Rt); imm32 = ZeroExtend(imm12, 32); add = (U == '1');
6549 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32);
6679 // t = UInt(Rt); imm32 = ZeroExtend(imm12, 32); add = (U == '1');
6963 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32);
7107 // t = UInt(Rt); imm32 = ZeroExtend(imm12, 32); add = (U == '1');
7364 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32);
7519 // t = UInt(Rt); imm32 = ZeroExtend(imm12, 32); add = (U == '1');
8296 imm32 = ARMExpandImm_C(opcode, APSR_C, carry); // (imm32, carry) = ARMExpandImm(imm12, APSR.C)
8463 imm32 = ARMExpandImm_C(opcode, APSR_C, carry); // (imm32, carry) = ARMExpandImm(imm12, APSR.C)
8627 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
8765 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
8902 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
9137 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
9204 imm32 = ARMExpandImm_C (opcode, APSR_C, carry); // (imm32, carry) = ARMExpandImm(imm12, APSR.C)
9329 imm32 = ARMExpandImm_C(opcode, APSR_C, carry); // (imm32, carry) = ARMExpandImm(imm12, APSR.C)
9885 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32);
9983 // if Rn == ?1101? && P == ?1? && U == ?0? && W == ?1? && imm12 == ?000000000100? then SEE PUSH;
9984 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32);
12127 // n = UInt(Rn); imm32 = ARMExpandImm(imm12); register_form = FALSE;
12286 // if Rn == '1101' && imm12 == '000000000100' then SEE PUSH;
12287 { 0x0e5f0000, 0x040d0000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTRRtSP, "str Rt, [sp, #-imm12]!" },
12428 { 0x0e500000, 0x04100000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRImmediateARM, "ldr<c> <Rt> [<Rn> {#+/-<imm12>}]" },
12460 { 0x0e500000, 0x04400000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTRBImmARM, "strb<c> <Rt>,[<Rn>,#+/-<imm12>]!"},
12461 { 0x0e500000, 0x04000000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTRImmARM, "str<c> <Rt>,[<Rn>,#+/-<imm12>]!"},
12523 { 0xfbff8f00, 0xf2ad0d00, ARMV6T2_ABOVE, eEncodingT3, No_VFP, eSize32, &EmulateInstructionARM::EmulateSUBSPImm, "subw sp, sp, #imm12"},
12632 { 0xfbf08000, 0xf2000000, ARMV6T2_ABOVE, eEncodingT4, No_VFP, eSize32, &EmulateInstructionARM::EmulateADDImmThumb, "addw<c> <Rd>,<Rn>,#<imm12>" },
12637 { 0xfbf08000, 0xf2a00000, ARMV6T2_ABOVE, eEncodingT4, No_VFP, eSize32, &EmulateInstructionARM::EmulateSUBImmThumb, "subw<c> <Rd>, <Rn>, #imm12"},
12640 { 0xfbff8000, 0xf2ad0000, ARMV6T2_ABOVE, eEncodingT3, No_VFP, eSize32, &EmulateInstructionARM::EmulateSUBSPImm, "subw<c> <Rd>, sp, #imm12"},
12731 { 0xfff00000, 0xf8d00000, ARMV6T2_ABOVE, eEncodingT3, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRRtRnImm, "ldr<c>.w <Rt>, [<Rn>{,#imm12}]"},
12738 { 0xfff00000, 0xf8900000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRBImmediate, "ldrb<c>.w <Rt>,[<Rn>{,#<imm12>}]" },
12744 { 0xfff00000, 0xf8b00000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRHImmediate, "ldrh<c>.w <Rt>,[<Rn>{,#<imm12>}]" },
12749 { 0xfff00000, 0xf9900000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRSBImmediate, "ldrsb<c> <Rt>,[<Rn>,#<imm12>]" },
12754 { 0xfff00000, 0xf9b00000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRSHImmediate, "ldrsh<c> <Rt>,[<Rn>,#<imm12>]" },
12776 { 0xfff00000, 0xf8c00000, ARMV6T2_ABOVE, eEncodingT3, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTRThumb, "str<c>.w <Rt>, [<Rn>,#<imm12>]" },
12781 { 0xfff00000, 0xf8800000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTRBThumb, "strb<c>.w <Rt>, [<Rn>, #<imm12>]" },
