Lines Matching refs:FPU
264 m_state.context.fpu.avx.__fpu_reserved[0] = -1;
265 m_state.context.fpu.avx.__fpu_reserved[1] = -1;
266 *(uint16_t *)&(m_state.context.fpu.avx.__fpu_fcw) = 0x1234;
267 *(uint16_t *)&(m_state.context.fpu.avx.__fpu_fsw) = 0x5678;
268 m_state.context.fpu.avx.__fpu_ftw = 1;
269 m_state.context.fpu.avx.__fpu_rsrv1 = UINT8_MAX;
270 m_state.context.fpu.avx.__fpu_fop = 2;
271 m_state.context.fpu.avx.__fpu_ip = 3;
272 m_state.context.fpu.avx.__fpu_cs = 4;
273 m_state.context.fpu.avx.__fpu_rsrv2 = 5;
274 m_state.context.fpu.avx.__fpu_dp = 6;
275 m_state.context.fpu.avx.__fpu_ds = 7;
276 m_state.context.fpu.avx.__fpu_rsrv3 = UINT16_MAX;
277 m_state.context.fpu.avx.__fpu_mxcsr = 8;
278 m_state.context.fpu.avx.__fpu_mxcsrmask = 9;
284 m_state.context.fpu.avx.__fpu_stmm0.__mmst_reg[i] = 'a';
285 m_state.context.fpu.avx.__fpu_stmm1.__mmst_reg[i] = 'b';
286 m_state.context.fpu.avx.__fpu_stmm2.__mmst_reg[i] = 'c';
287 m_state.context.fpu.avx.__fpu_stmm3.__mmst_reg[i] = 'd';
288 m_state.context.fpu.avx.__fpu_stmm4.__mmst_reg[i] = 'e';
289 m_state.context.fpu.avx.__fpu_stmm5.__mmst_reg[i] = 'f';
290 m_state.context.fpu.avx.__fpu_stmm6.__mmst_reg[i] = 'g';
291 m_state.context.fpu.avx.__fpu_stmm7.__mmst_reg[i] = 'h';
295 m_state.context.fpu.avx.__fpu_stmm0.__mmst_reg[i] = INT8_MIN;
296 m_state.context.fpu.avx.__fpu_stmm1.__mmst_reg[i] = INT8_MIN;
297 m_state.context.fpu.avx.__fpu_stmm2.__mmst_reg[i] = INT8_MIN;
298 m_state.context.fpu.avx.__fpu_stmm3.__mmst_reg[i] = INT8_MIN;
299 m_state.context.fpu.avx.__fpu_stmm4.__mmst_reg[i] = INT8_MIN;
300 m_state.context.fpu.avx.__fpu_stmm5.__mmst_reg[i] = INT8_MIN;
301 m_state.context.fpu.avx.__fpu_stmm6.__mmst_reg[i] = INT8_MIN;
302 m_state.context.fpu.avx.__fpu_stmm7.__mmst_reg[i] = INT8_MIN;
305 m_state.context.fpu.avx.__fpu_xmm0.__xmm_reg[i] = '0';
306 m_state.context.fpu.avx.__fpu_xmm1.__xmm_reg[i] = '1';
307 m_state.context.fpu.avx.__fpu_xmm2.__xmm_reg[i] = '2';
308 m_state.context.fpu.avx.__fpu_xmm3.__xmm_reg[i] = '3';
309 m_state.context.fpu.avx.__fpu_xmm4.__xmm_reg[i] = '4';
310 m_state.context.fpu.avx.__fpu_xmm5.__xmm_reg[i] = '5';
311 m_state.context.fpu.avx.__fpu_xmm6.__xmm_reg[i] = '6';
312 m_state.context.fpu.avx.__fpu_xmm7.__xmm_reg[i] = '7';
313 m_state.context.fpu.avx.__fpu_xmm8.__xmm_reg[i] = '8';
314 m_state.context.fpu.avx.__fpu_xmm9.__xmm_reg[i] = '9';
315 m_state.context.fpu.avx.__fpu_xmm10.__xmm_reg[i] = 'A';
316 m_state.context.fpu.avx.__fpu_xmm11.__xmm_reg[i] = 'B';
317 m_state.context.fpu.avx.__fpu_xmm12.__xmm_reg[i] = 'C';
318 m_state.context.fpu.avx.__fpu_xmm13.__xmm_reg[i] = 'D';
319 m_state.context.fpu.avx.__fpu_xmm14.__xmm_reg[i] = 'E';
320 m_state.context.fpu.avx.__fpu_xmm15.__xmm_reg[i] = 'F';
322 m_state.context.fpu.avx.__fpu_ymmh0.__xmm_reg[i] = '0';
323 m_state.context.fpu.avx.__fpu_ymmh1.__xmm_reg[i] = '1';
324 m_state.context.fpu.avx.__fpu_ymmh2.__xmm_reg[i] = '2';
325 m_state.context.fpu.avx.__fpu_ymmh3.__xmm_reg[i] = '3';
326 m_state.context.fpu.avx.__fpu_ymmh4.__xmm_reg[i] = '4';
327 m_state.context.fpu.avx.__fpu_ymmh5.__xmm_reg[i] = '5';
328 m_state.context.fpu.avx.__fpu_ymmh6.__xmm_reg[i] = '6';
329 m_state.context.fpu.avx.__fpu_ymmh7.__xmm_reg[i] = '7';
330 m_state.context.fpu.avx.__fpu_ymmh8.__xmm_reg[i] = '8';
331 m_state.context.fpu.avx.__fpu_ymmh9.__xmm_reg[i] = '9';
332 m_state.context.fpu.avx.__fpu_ymmh10.__xmm_reg[i] = 'A';
333 m_state.context.fpu.avx.__fpu_ymmh11.__xmm_reg[i] = 'B';
334 m_state.context.fpu.avx.__fpu_ymmh12.__xmm_reg[i] = 'C';
335 m_state.context.fpu.avx.__fpu_ymmh13.__xmm_reg[i] = 'D';
336 m_state.context.fpu.avx.__fpu_ymmh14.__xmm_reg[i] = 'E';
337 m_state.context.fpu.avx.__fpu_ymmh15.__xmm_reg[i] = 'F';
339 for (i=0; i<sizeof(m_state.context.fpu.avx.__fpu_rsrv4); ++i)
340 m_state.context.fpu.avx.__fpu_rsrv4[i] = INT8_MIN;
341 m_state.context.fpu.avx.__fpu_reserved1 = -1;
342 for (i=0; i<sizeof(m_state.context.fpu.avx.__avx_reserved1); ++i)
343 m_state.context.fpu.avx.__avx_reserved1[i] = INT8_MIN;
348 m_state.context.fpu.no_avx.__fpu_reserved[0] = -1;
349 m_state.context.fpu.no_avx.__fpu_reserved[1] = -1;
350 *(uint16_t *)&(m_state.context.fpu.no_avx.__fpu_fcw) = 0x1234;
351 *(uint16_t *)&(m_state.context.fpu.no_avx.__fpu_fsw) = 0x5678;
352 m_state.context.fpu.no_avx.__fpu_ftw = 1;
353 m_state.context.fpu.no_avx.__fpu_rsrv1 = UINT8_MAX;
354 m_state.context.fpu.no_avx.__fpu_fop = 2;
355 m_state.context.fpu.no_avx.__fpu_ip = 3;
356 m_state.context.fpu
357 m_state.context.fpu.no_avx.__fpu_rsrv2 = 5;
358 m_state.context.fpu.no_avx.__fpu_dp = 6;
359 m_state.context.fpu.no_avx.__fpu_ds = 7;
360 m_state.context.fpu.no_avx.__fpu_rsrv3 = UINT16_MAX;
361 m_state.context.fpu.no_avx.__fpu_mxcsr = 8;
362 m_state.context.fpu.no_avx.__fpu_mxcsrmask = 9;
368 m_state.context.fpu.no_avx.__fpu_stmm0.__mmst_reg[i] = 'a';
369 m_state.context.fpu.no_avx.__fpu_stmm1.__mmst_reg[i] = 'b';
370 m_state.context.fpu.no_avx.__fpu_stmm2.__mmst_reg[i] = 'c';
371 m_state.context.fpu.no_avx.__fpu_stmm3.__mmst_reg[i] = 'd';
372 m_state.context.fpu.no_avx.__fpu_stmm4.__mmst_reg[i] = 'e';
373 m_state.context.fpu.no_avx.__fpu_stmm5.__mmst_reg[i] = 'f';
374 m_state.context.fpu.no_avx.__fpu_stmm6.__mmst_reg[i] = 'g';
375 m_state.context.fpu.no_avx.__fpu_stmm7.__mmst_reg[i] = 'h';
379 m_state.context.fpu.no_avx.__fpu_stmm0.__mmst_reg[i] = INT8_MIN;
380 m_state.context.fpu.no_avx.__fpu_stmm1.__mmst_reg[i] = INT8_MIN;
381 m_state.context.fpu.no_avx.__fpu_stmm2.__mmst_reg[i] = INT8_MIN;
382 m_state.context.fpu.no_avx.__fpu_stmm3.__mmst_reg[i] = INT8_MIN;
383 m_state.context.fpu.no_avx.__fpu_stmm4.__mmst_reg[i] = INT8_MIN;
384 m_state.context.fpu.no_avx.__fpu_stmm5.__mmst_reg[i] = INT8_MIN;
385 m_state.context.fpu.no_avx.__fpu_stmm6.__mmst_reg[i] = INT8_MIN;
386 m_state.context.fpu.no_avx.__fpu_stmm7.__mmst_reg[i] = INT8_MIN;
389 m_state.context.fpu.no_avx.__fpu_xmm0.__xmm_reg[i] = '0';
390 m_state.context.fpu.no_avx.__fpu_xmm1.__xmm_reg[i] = '1';
391 m_state.context.fpu.no_avx.__fpu_xmm2.__xmm_reg[i] = '2';
392 m_state.context.fpu.no_avx.__fpu_xmm3.__xmm_reg[i] = '3';
393 m_state.context.fpu.no_avx.__fpu_xmm4.__xmm_reg[i] = '4';
394 m_state.context.fpu.no_avx.__fpu_xmm5.__xmm_reg[i] = '5';
395 m_state.context.fpu.no_avx.__fpu_xmm6.__xmm_reg[i] = '6';
396 m_state.context.fpu.no_avx.__fpu_xmm7.__xmm_reg[i] = '7';
397 m_state.context.fpu.no_avx.__fpu_xmm8.__xmm_reg[i] = '8';
398 m_state.context.fpu.no_avx.__fpu_xmm9.__xmm_reg[i] = '9';
399 m_state.context.fpu.no_avx.__fpu_xmm10.__xmm_reg[i] = 'A';
400 m_state.context.fpu.no_avx.__fpu_xmm11.__xmm_reg[i] = 'B';
401 m_state.context.fpu.no_avx.__fpu_xmm12.__xmm_reg[i] = 'C';
402 m_state.context.fpu.no_avx.__fpu_xmm13.__xmm_reg[i] = 'D';
403 m_state.context.fpu.no_avx.__fpu_xmm14.__xmm_reg[i] = 'E';
404 m_state.context.fpu.no_avx.__fpu_xmm15.__xmm_reg[i] = 'F';
406 for (i=0; i<sizeof(m_state.context.fpu.no_avx.__fpu_rsrv4); ++i)
407 m_state.context.fpu.no_avx.__fpu_rsrv4[i] = INT8_MIN;
408 m_state.context.fpu.no_avx.__fpu_reserved1 = -1;
417 m_state.SetError(e_regSetFPU, Read, ::thread_get_state(m_thread->MachPortNumber(), __x86_64_AVX_STATE, (thread_state_t)&m_state.context.fpu.avx, &count));
425 m_state.SetError(e_regSetFPU, Read, ::thread_get_state(m_thread->MachPortNumber(), __x86_64_FLOAT_STATE, (thread_state_t)&m_state.context.fpu.no_avx, &count));
426 DNBLogThreadedIf (LOG_THREAD, "::thread_get_state (0x%4.4x, %u, &fpu, %u (%u passed in) => 0x%8.8x",
484 m_state.SetError(e_regSetFPU, Write, ::thread_set_state(m_thread->MachPortNumber(), __x86_64_AVX_STATE, (thread_state_t)&m_state.context.fpu.avx, e_regSetWordSizeAVX));
489 m_state.SetError(e_regSetFPU, Write, ::thread_set_state(m_thread->MachPortNumber(), __x86_64_FLOAT_STATE, (thread_state_t)&m_state.context.fpu.no_avx, e_regSetWordSizeFPU));
1256 #define FPU_OFFSET(reg) (offsetof (DNBArchImplX86_64::FPU, __fpu_##reg) + offsetof (DNBArchImplX86_64::Context, fpu.no_avx))
1257 #define AVX_OFFSET(reg) (offsetof (DNBArchImplX86_64::AVX, __fpu_##reg) + offsetof (DNBArchImplX86_64::Context, fpu.avx))
1261 // Context.fpu.avx. That is because there is a bunch of padding
1262 // in Context.fpu.avx that we don't need. Offset macros lay out
1268 #define FPU_SIZE_UINT(reg) (sizeof(((DNBArchImplX86_64::FPU *)NULL)->__fpu_##reg))
1269 #define FPU_SIZE_MMST(reg) (sizeof(((DNBArchImplX86_64::FPU *)NULL)->__fpu_##reg.__mmst_reg))
1270 #define FPU_SIZE_XMM(reg) (sizeof(((DNBArchImplX86_64::FPU *)NULL)->__fpu_##reg.__xmm_reg))
1645 case fpu_fcw: value->value.uint16 = *((uint16_t *)(&m_state.context.fpu.avx.__fpu_fcw)); return true;
1646 case fpu_fsw: value->value.uint16 = *((uint16_t *)(&m_state.context.fpu.avx.__fpu_fsw)); return true;
1647 case fpu_ftw: value->value.uint8 = m_state.context.fpu.avx.__fpu_ftw; return true;
1648 case fpu_fop: value->value.uint16 = m_state.context.fpu.avx.__fpu_fop; return true;
1649 case fpu_ip: value->value.uint32 = m_state.context.fpu.avx.__fpu_ip; return true;
1650 case fpu_cs: value->value.uint16 = m_state.context.fpu.avx.__fpu_cs; return true;
1651 case fpu_dp: value->value.uint32 = m_state.context.fpu.avx.__fpu_dp; return true;
1652 case fpu_ds: value->value.uint16 = m_state.context.fpu.avx.__fpu_ds; return true;
1653 case fpu_mxcsr: value->value.uint32 = m_state.context.fpu.avx.__fpu_mxcsr; return true;
1654 case fpu_mxcsrmask: value->value.uint32 = m_state.context.fpu.avx.__fpu_mxcsrmask; return true;
1664 memcpy(&value->value.uint8, &m_state.context.fpu.avx.__fpu_stmm0 + (reg - fpu_stmm0), 10);
1683 memcpy(&value->value.uint8, &m_state.context.fpu.avx.__fpu_xmm0 + (reg - fpu_xmm0), 16);
1702 memcpy(&value->value.uint8, &m_state.context.fpu.avx.__fpu_xmm0 + (reg - fpu_ymm0), 16);
1703 memcpy((&value->value.uint8) + 16, &m_state.context.fpu.avx.__fpu_ymmh0 + (reg - fpu_ymm0), 16);
1711 case fpu_fcw: value->value.uint16 = *((uint16_t *)(&m_state.context.fpu.no_avx.__fpu_fcw)); return true;
1712 case fpu_fsw: value->value.uint16 = *((uint16_t *)(&m_state.context.fpu.no_avx.__fpu_fsw)); return true;
1713 case fpu_ftw: value->value.uint8 = m_state.context.fpu.no_avx.__fpu_ftw; return true;
1714 case fpu_fop: value->value.uint16 = m_state.context.fpu.no_avx.__fpu_fop; return true;
1715 case fpu_ip: value->value.uint32 = m_state.context.fpu.no_avx.__fpu_ip; return true;
1716 case fpu_cs: value->value.uint16 = m_state.context.fpu.no_avx.__fpu_cs; return true;
1717 case fpu_dp: value->value.uint32 = m_state.context.fpu.no_avx.__fpu_dp; return true;
1718 case fpu_ds: value->value.uint16 = m_state.context.fpu.no_avx.__fpu_ds; return true;
1719 case fpu_mxcsr: value->value.uint32 = m_state.context.fpu.no_avx.__fpu_mxcsr; return true;
1720 case fpu_mxcsrmask: value->value.uint32 = m_state.context.fpu.no_avx.__fpu_mxcsrmask; return true;
1730 memcpy(&value->value.uint8, &m_state.context.fpu.no_avx.__fpu_stmm0 + (reg - fpu_stmm0), 10);
1749 memcpy(&value->value.uint8, &m_state.context.fpu.no_avx.__fpu_xmm0 + (reg - fpu_xmm0), 16);
1824 case fpu_fcw: *((uint16_t *)(&m_state.context.fpu.avx.__fpu_fcw)) = value->value.uint16; success = true; break;
1825 case fpu_fsw: *((uint16_t *)(&m_state.context.fpu.avx.__fpu_fsw)) = value->value.uint16; success = true; break;
1826 case fpu_ftw: m_state.context.fpu.avx.__fpu_ftw = value->value.uint8; success = true; break;
1827 case fpu_fop: m_state.context.fpu.avx.__fpu_fop = value->value.uint16; success = true; break;
1828 case fpu_ip: m_state.context.fpu.avx.__fpu_ip = value->value.uint32; success = true; break;
1829 case fpu_cs: m_state.context.fpu.avx.__fpu_cs = value->value.uint16; success = true; break;
1830 case fpu_dp: m_state.context.fpu.avx.__fpu_dp = value->value.uint32; success = true; break;
1831 case fpu_ds: m_state.context.fpu.avx.__fpu_ds = value->value.uint16; success = true; break;
1832 case fpu_mxcsr: m_state.context.fpu.avx.__fpu_mxcsr = value->value.uint32; success = true; break;
1833 case fpu_mxcsrmask: m_state.context.fpu.avx.__fpu_mxcsrmask = value->value.uint32; success = true; break;
1843 memcpy (&m_state.context.fpu.avx.__fpu_stmm0 + (reg - fpu_stmm0), &value->value.uint8, 10);
1863 memcpy (&m_state.context.fpu.avx.__fpu_xmm0 + (reg - fpu_xmm0), &value->value.uint8, 16);
1883 memcpy(&m_state.context.fpu.avx.__fpu_xmm0 + (reg - fpu_ymm0), &value->value.uint8, 16);
1884 memcpy(&m_state.context.fpu.avx.__fpu_ymmh0 + (reg - fpu_ymm0), (&value->value.uint8) + 16, 16);
1892 case fpu_fcw: *((uint16_t *)(&m_state.context.fpu.no_avx.__fpu_fcw)) = value->value.uint16; success = true; break;
1893 case fpu_fsw: *((uint16_t *)(&m_state.context.fpu.no_avx.__fpu_fsw)) = value->value.uint16; success = true; break;
1894 case fpu_ftw: m_state.context.fpu.no_avx.__fpu_ftw = value->value.uint8; success = true; break;
1895 case fpu_fop: m_state.context.fpu.no_avx.__fpu_fop = value->value.uint16; success = true; break;
1896 case fpu_ip: m_state.context.fpu.no_avx.__fpu_ip = value->value.uint32; success = true; break;
1897 case fpu_cs: m_state.context.fpu.no_avx.__fpu_cs = value->value.uint16; success = true; break;
1898 case fpu_dp: m_state.context.fpu.no_avx.__fpu_dp = value->value.uint32; success = true; break;
1899 case fpu_ds: m_state.context.fpu.no_avx.__fpu_ds = value->value.uint16; success = true; break;
1900 case fpu_mxcsr: m_state.context.fpu.no_avx.__fpu_mxcsr = value->value.uint32; success = true; break;
1901 case fpu_mxcsrmask: m_state.context.fpu.no_avx.__fpu_mxcsrmask = value->value.uint32; success = true; break;
1911 memcpy (&m_state.context.fpu.no_avx.__fpu_stmm0 + (reg - fpu_stmm0), &value->value.uint8, 10);
1931 memcpy (&m_state.context.fpu.no_avx.__fpu_xmm0 + (reg - fpu_xmm0), &value->value.uint8, 16);
1975 DNBLogThreadedIf (LOG_THREAD, "DNBArchImplX86_64::GetRegisterContext (buf = %p, len = %llu) error: %s regs failed to read: %u", buf, (uint64_t)buf_len, CPUHasAVX() ? "AVX" : "FPU", kret);
2012 DNBLogThreadedIf (LOG_THREAD, "DNBArchImplX86_64::SetRegisterContext (buf = %p, len = %llu) error: %s regs failed to write: %u", buf, (uint64_t)buf_len, CPUHasAVX() ? "AVX" : "FPU", kret);
