Lines Matching defs:VirtReg
73 unsigned VirtReg; // Virtual register number.
79 : LastUse(nullptr), VirtReg(v), PhysReg(0), LastOpNum(0), Dirty(false){}
82 return TargetRegisterInfo::virtReg2Index(VirtReg);
114 // PhysRegState - One of the RegState enums, or a virtreg.
168 int getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC);
173 void killVirtReg(unsigned VirtReg);
175 void spillVirtReg(MachineBasicBlock::iterator MI, unsigned VirtReg);
181 LiveRegMap::iterator findLiveVirtReg(unsigned VirtReg) {
182 return LiveVirtRegs.find(TargetRegisterInfo::virtReg2Index(VirtReg));
184 LiveRegMap::const_iterator findLiveVirtReg(unsigned VirtReg) const {
185 return LiveVirtRegs.find(TargetRegisterInfo::virtReg2Index(VirtReg));
191 unsigned VirtReg, unsigned Hint);
193 unsigned VirtReg, unsigned Hint);
202 int RAFast::getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC) {
204 int SS = StackSlotForVirtReg[VirtReg];
213 StackSlotForVirtReg[VirtReg] = FrameIdx;
245 /// killVirtReg - Mark virtreg as no longer available.
248 assert(PhysRegState[LRI->PhysReg] == LRI->VirtReg &&
256 /// killVirtReg - Mark virtreg as no longer available.
257 void RAFast::killVirtReg(unsigned VirtReg) {
258 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
260 LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg);
265 /// spillVirtReg - This method spills the value specified by VirtReg into the
267 void RAFast::spillVirtReg(MachineBasicBlock::iterator MI, unsigned VirtReg) {
268 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
270 LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg);
279 assert(PhysRegState[LR.PhysReg] == LRI->VirtReg && "Broken RegState mapping");
286 DEBUG(dbgs() << "Spilling " << PrintReg(LRI->VirtReg, TRI)
288 const TargetRegisterClass *RC = MRI->getRegClass(LRI->VirtReg);
289 int FI = getStackSpaceFor(LRI->VirtReg, RC);
298 LiveDbgValueMap[LRI->VirtReg];
332 // The LiveRegMap is keyed by an unsigned (the virtreg number), so the order
342 /// Check that the register is not used by a virtreg.
403 switch (unsigned VirtReg = PhysRegState[PhysReg]) {
407 spillVirtReg(MI, VirtReg);
419 switch (unsigned VirtReg = PhysRegState[Alias]) {
423 spillVirtReg(MI, VirtReg);
446 switch (unsigned VirtReg = PhysRegState[PhysReg]) {
452 DEBUG(dbgs() << PrintReg(VirtReg, TRI) << " corresponding "
456 LiveRegMap::const_iterator I = findLiveVirtReg(VirtReg);
457 assert(I != LiveVirtRegs.end() && "Missing VirtReg entry");
467 switch (unsigned VirtReg = PhysRegState[Alias]) {
476 LiveRegMap::const_iterator I = findLiveVirtReg(VirtReg);
477 assert(I != LiveVirtRegs.end() && "Missing VirtReg entry");
488 /// that PhysReg is the proper container for VirtReg now. The physical
492 DEBUG(dbgs() << "Assigning " << PrintReg(LR.VirtReg, TRI) << " to "
494 PhysRegState[PhysReg] = LR.VirtReg;
500 RAFast::assignVirtToPhysReg(unsigned VirtReg, unsigned PhysReg) {
501 LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg);
502 assert(LRI != LiveVirtRegs.end() && "VirtReg disappeared");
507 /// allocVirtReg - Allocate a physical register for VirtReg.
511 const unsigned VirtReg = LRI->VirtReg;
513 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
516 const TargetRegisterClass *RC = MRI->getRegClass(VirtReg);
531 // That invalidates LRI, so run a new lookup for VirtReg.
532 return assignVirtToPhysReg(VirtReg, Hint);
547 DEBUG(dbgs() << "Allocating " << PrintReg(VirtReg) << " from "
568 // That invalidates LRI, so run a new lookup for VirtReg.
569 return assignVirtToPhysReg(VirtReg, BestReg);
578 return assignVirtToPhysReg(VirtReg, *AO.begin());
581 /// defineVirtReg - Allocate a register for VirtReg and mark it as dirty.
584 unsigned VirtReg, unsigned Hint) {
585 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
589 std::tie(LRI, New) = LiveVirtRegs.insert(LiveReg(VirtReg));
593 MRI->hasOneNonDBGUse(VirtReg)) {
594 const MachineInstr &UseMI = *MRI->use_instr_nodbg_begin(VirtReg);
602 // instruction defining VirtReg multiple times.
614 /// reloadVirtReg - Make sure VirtReg is available in a physreg and return it.
617 unsigned VirtReg, unsigned Hint) {
618 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
622 std::tie(LRI, New) = LiveVirtRegs.insert(LiveReg(VirtReg));
626 const TargetRegisterClass *RC = MRI->getRegClass(VirtReg);
627 int FrameIndex = getStackSpaceFor(VirtReg, RC);
628 DEBUG(dbgs() << "Reloading " << PrintReg(VirtReg, TRI) << " into "
821 assert(I != LiveVirtRegs.end() && "Missing VirtReg entry");
833 assert(TargetRegisterInfo::isVirtualRegister(i->VirtReg) &&
837 assert(PhysRegState[i->PhysReg] == i->VirtReg && "Bad inverse map");
901 // Find the end of the virtreg operands
961 // Allocate virtreg uses.
