Lines Matching refs:ISD
172 /// \brief Replace an ISD::EXTRACT_VECTOR_ELT of a load with a narrowed
175 /// \param EVE ISD::EXTRACT_VECTOR_ELT to be replaced.
193 ISD::NodeType ExtType);
293 SDValue N3, ISD::CondCode CC,
295 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
453 if (Op.getOpcode() == ISD::FNEG) return 2;
463 case ISD::ConstantFP:
467 case ISD::FADD:
473 !TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType()))
483 case ISD::FSUB:
490 case ISD::FMUL:
491 case ISD::FDIV:
502 case ISD::FP_EXTEND:
503 case ISD::FP_ROUND:
504 case ISD::FSIN:
515 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0);
523 case ISD::ConstantFP: {
528 case ISD::FADD:
536 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(),
541 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(),
545 case ISD::FSUB:
555 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(),
558 case ISD::FMUL:
559 case ISD::FDIV:
577 case ISD::FP_EXTEND:
578 case ISD::FSIN:
582 case ISD::FP_ROUND:
583 return DAG.getNode(ISD::FP_ROUND, SDLoc(Op), Op.getValueType(),
597 if (N.getOpcode() == ISD::SETCC) {
604 if (N.getOpcode() != ISD::SELECT_CC ||
813 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, VT, SDValue(ExtLoad, 0));
833 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD)
834 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD
835 : ISD::EXTLOAD)
846 case ISD::AssertSext:
847 return DAG.getNode(ISD::AssertSext, dl, PVT,
850 case ISD::AssertZext:
851 return DAG.getNode(ISD::AssertZext, dl, PVT,
854 case ISD::Constant: {
856 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
861 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT))
863 return DAG.getNode(ISD::ANY_EXTEND, dl, PVT, Op);
867 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT))
879 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NewOp.getValueType(), NewOp,
949 return DAG.getNode(ISD::TRUNCATE, dl, VT,
980 if (Opc == ISD::SRA)
982 else if (Opc == ISD::SRL)
996 return DAG.getNode(ISD::TRUNCATE, dl, VT,
1055 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD)
1056 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD
1057 : ISD::EXTLOAD)
1062 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, VT, NewLD);
1143 assert(N->getOpcode() != ISD::DELETED_NODE &&
1144 RV.getNode()->getOpcode() != ISD::DELETED_NODE &&
1196 case ISD::TokenFactor: return visitTokenFactor(N);
1197 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N);
1198 case ISD::ADD: return visitADD(N);
1199 case ISD::SUB: return visitSUB(N);
1200 case ISD::ADDC: return visitADDC(N);
1201 case ISD::SUBC: return visitSUBC(N);
1202 case ISD::ADDE: return visitADDE(N);
1203 case ISD::SUBE: return visitSUBE(N);
1204 case ISD::MUL: return visitMUL(N);
1205 case ISD::SDIV: return visitSDIV(N);
1206 case ISD::UDIV: return visitUDIV(N);
1207 case ISD::SREM: return visitSREM(N);
1208 case ISD::UREM: return visitUREM(N);
1209 case ISD::MULHU: return visitMULHU(N);
1210 case ISD::MULHS: return visitMULHS(N);
1211 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N);
1212 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N);
1213 case ISD::SMULO: return visitSMULO(N);
1214 case ISD::UMULO: return visitUMULO(N);
1215 case ISD::SDIVREM: return visitSDIVREM(N);
1216 case ISD::UDIVREM: return visitUDIVREM(N);
1217 case ISD::AND: return visitAND(N);
1218 case ISD::OR: return visitOR(N);
1219 case ISD::XOR: return visitXOR(N);
1220 case ISD::SHL: return visitSHL(N);
1221 case ISD::SRA: return visitSRA(N);
1222 case ISD::SRL: return visitSRL(N);
1223 case ISD::ROTR:
1224 case ISD::ROTL: return visitRotate(N);
1225 case ISD::CTLZ: return visitCTLZ(N);
1226 case ISD::CTLZ_ZERO_UNDEF: return visitCTLZ_ZERO_UNDEF(N);
1227 case ISD::CTTZ: return visitCTTZ(N);
1228 case ISD::CTTZ_ZERO_UNDEF: return visitCTTZ_ZERO_UNDEF(N);
1229 case ISD::CTPOP: return visitCTPOP(N);
1230 case ISD::SELECT: return visitSELECT(N);
1231 case ISD::VSELECT: return visitVSELECT(N);
1232 case ISD::SELECT_CC: return visitSELECT_CC(N);
1233 case ISD::SETCC: return visitSETCC(N);
1234 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
1235 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
1236 case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
1237 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
1238 case ISD::TRUNCATE: return visitTRUNCATE(N);
1239 case ISD::BITCAST: return visitBITCAST(N);
1240 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N);
1241 case ISD::FADD: return visitFADD(N);
1242 case ISD::FSUB: return visitFSUB(N);
1243 case ISD::FMUL: return visitFMUL(N);
1244 case ISD::FMA: return visitFMA(N);
1245 case ISD::FDIV: return visitFDIV(N);
1246 case ISD::FREM: return visitFREM(N);
1247 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
1248 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
1249 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
1250 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
1251 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
1252 case ISD::FP_ROUND: return visitFP_ROUND(N);
1253 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
1254 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
1255 case ISD::FNEG: return visitFNEG(N);
1256 case ISD::FABS: return visitFABS(N);
1257 case ISD::FFLOOR: return visitFFLOOR(N);
1258 case ISD::FCEIL: return visitFCEIL(N);
1259 case ISD::FTRUNC: return visitFTRUNC(N);
1260 case ISD::BRCOND: return visitBRCOND(N);
1261 case ISD::BR_CC: return visitBR_CC(N);
1262 case ISD::LOAD: return visitLOAD(N);
1263 case ISD::STORE: return visitSTORE(N);
1264 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
1265 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N);
1266 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N);
1267 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N);
1268 case ISD::EXTRACT_SUBVECTOR: return visitEXTRACT_SUBVECTOR(N);
1269 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
1270 case ISD::INSERT_SUBVECTOR: return visitINSERT_SUBVECTOR(N);
1280 assert(N->getOpcode() != ISD::DELETED_NODE &&
1283 if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
1284 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) {
1298 case ISD::ADD:
1299 case ISD::SUB:
1300 case ISD::MUL:
1301 case ISD::AND:
1302 case ISD::OR:
1303 case ISD::XOR:
1306 case ISD::SHL:
1307 case ISD::SRA:
1308 case ISD::SRL:
1311 case ISD::SIGN_EXTEND:
1312 case ISD::ZERO_EXTEND:
1313 case ISD::ANY_EXTEND:
1316 case ISD::LOAD:
1393 case ISD::EntryToken:
1399 case ISD::TokenFactor:
1431 Result = DAG.getNode(ISD::TokenFactor, SDLoc(N), MVT::Other, Ops);
1467 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() &&
1470 N0 = DAG.getNode(ISD::ADD, SDLoc(N0), VT,
1471 DAG.getNode(ISD::SHL, SDLoc(N00), VT,
1473 DAG.getNode(ISD::SHL, SDLoc(N01), VT,
1475 return DAG.getNode(ISD::ADD, DL, VT, N0, N1);
1494 if (ISD::isBuildVectorAllZeros(N1.getNode()))
1496 if (ISD::isBuildVectorAllZeros(N0.getNode()))
1501 if (N0.getOpcode() == ISD::UNDEF)
1503 if (N1.getOpcode() == ISD::UNDEF)
1507 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C);
1510 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N1, N0);
1517 GA->getOpcode() == ISD::GlobalAddress)
1522 if (N1C && N0.getOpcode() == ISD::SUB)
1524 return DAG.getNode(ISD::SUB, SDLoc(N), VT,
1529 SDValue RADD = ReassociateOps(ISD::ADD, SDLoc(N), N0, N1);
1533 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
1535 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N1, N0.getOperand(1));
1537 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
1539 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N0, N1.getOperand(1));
1541 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
1544 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1))
1547 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1549 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N1.getOperand(0),
1552 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1554 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N1.getOperand(0),
1557 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) &&
1558 N1.getOperand(0).getOpcode() == ISD::SUB &&
1564 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) {
1571 return DAG.getNode(ISD::SUB, SDLoc(N), VT,
1572 DAG.getNode(ISD::ADD, SDLoc(N0), VT, N00, N10),
1573 DAG.getNode(ISD::ADD, SDLoc(N1), VT, N01, N11));
1591 if (!LegalOperations || TLI.isOperationLegal(ISD::OR, VT))
1592 return DAG.getNode(ISD::OR, SDLoc(N), VT, N0, N1);
1598 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) {
1602 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) {
1608 if (N1.getOpcode() == ISD::SHL &&
1609 N1.getOperand(0).getOpcode() == ISD::SUB)
1613 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N0,
1614 DAG.getNode(ISD::SHL, SDLoc(N), VT,
1617 if (N0.getOpcode() == ISD::SHL &&
1618 N0.getOperand(0).getOpcode() == ISD::SUB)
1622 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N1,
1623 DAG.getNode(ISD::SHL, SDLoc(N), VT,
1627 if (N1.getOpcode() == ISD::AND) {
1637 return DAG.getNode(ISD::SUB, DL, VT, N->getOperand(0), AndOp0);
1642 if (N0.getOpcode() == ISD::SIGN_EXTEND &&
1644 !TLI.isOperationLegal(ISD::SIGN_EXTEND, MVT::i1)) {
1646 SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0));
1647 return DAG.getNode(ISD::SUB, DL, VT, N1, ZExt);
1662 return CombineTo(N, DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N1),
1663 DAG.getNode(ISD::CARRY_FALSE,
1668 return DAG.getNode(ISD::ADDC, SDLoc(N), N->getVTList(), N1, N0);
1672 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE,
1686 return CombineTo(N, DAG.getNode(ISD::OR, SDLoc(N), VT, N0, N1),
1687 DAG.getNode(ISD::CARRY_FALSE,
1703 return DAG.getNode(ISD::ADDE, SDLoc(N), N->getVTList(),
1707 if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
1708 return DAG.getNode(ISD::ADDC, SDLoc(N), N->getVTList(), N0, N1);
1720 if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT))
1730 ConstantSDNode *N1C1 = N1.getOpcode() != ISD::ADD ? nullptr :
1740 if (ISD::isBuildVectorAllZeros(N1.getNode()))
1750 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C);
1753 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0,
1757 return DAG.getNode(ISD::XOR, SDLoc(N), VT, N1, N0);
1759 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(0))
1762 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
1765 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
1768 if (N1.getOpcode() == ISD::ADD && N0C && N1C1) {
1771 return DAG.getNode(ISD::SUB, SDLoc(N), VT, NewC,
1775 if (N0.getOpcode() == ISD::ADD &&
1776 (N0.getOperand(1).getOpcode() == ISD::SUB ||
1777 N0.getOperand(1).getOpcode() == ISD::ADD) &&
1782 if (N0.getOpcode() == ISD::ADD &&
1783 N0.getOperand(1).getOpcode() == ISD::ADD &&
1785 return DAG.getNode(ISD::ADD, SDLoc(N), VT,
1788 if (N0.getOpcode() == ISD::SUB &&
1789 N0.getOperand(1).getOpcode() == ISD::SUB &&
1791 return DAG.getNode(ISD::SUB, SDLoc(N), VT,
1795 if (N0.getOpcode() == ISD::UNDEF)
1797 if (N1.getOpcode() == ISD::UNDEF)
1804 if (N1C && GA->getOpcode() == ISD::GlobalAddress)
1827 return CombineTo(N, DAG.getNode(ISD::SUB, SDLoc(N), VT, N0, N1),
1828 DAG.getNode(ISD::CARRY_FALSE, SDLoc(N),
1834 DAG.getNode(ISD::CARRY_FALSE, SDLoc(N),
1839 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, SDLoc(N),
1844 return CombineTo(N, DAG.getNode(ISD::XOR, SDLoc(N), VT, N1, N0),
1845 DAG.getNode(ISD::CARRY_FALSE, SDLoc(N),
1857 if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
1858 return DAG.getNode(ISD::SUBC, SDLoc(N), N->getVTList(), N0, N1);
1869 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1893 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0.getNode(), N1.getNode());
1897 return DAG.getNode(ISD::MUL, SDLoc(N), VT, N1, N0);
1910 return DAG.getNode(ISD::SUB, SDLoc(N), VT,
1914 return DAG.getNode(ISD::SHL, SDLoc(N), VT, N0,
1922 return DAG.getNode(ISD::SUB, SDLoc(N), VT,
1924 DAG.getNode(ISD::SHL, SDLoc(N), VT, N0,
1931 if (N1IsConst && N0.getOpcode() == ISD::SHL &&
1934 SDValue C3 = DAG.getNode(ISD::SHL, SDLoc(N), VT,
1937 return DAG.getNode(ISD::MUL, SDLoc(N), VT,
1946 if (N0.getOpcode() == ISD::SHL &&
1951 } else if (N1.getOpcode() == ISD::SHL &&
1958 SDValue Mul = DAG.getNode(ISD::MUL, SDLoc(N), VT,
1960 return DAG.getNode(ISD::SHL, SDLoc(N), VT,
1966 if (N1IsConst && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() &&
1969 return DAG.getNode(ISD::ADD, SDLoc(N), VT,
1970 DAG.getNode(ISD::MUL, SDLoc(N0), VT,
1972 DAG.getNode(ISD::MUL, SDLoc(N1), VT,
1976 SDValue RMUL = ReassociateOps(ISD::MUL, SDLoc(N), N0, N1);
1998 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C);
2004 return DAG.getNode(ISD::SUB, SDLoc(N), VT,
2010 return DAG.getNode(ISD::UDIV, SDLoc(N), N1.getValueType(),
2026 DAG.getNode(ISD::SRA, SDLoc(N), VT, N0,
2033 DAG.getNode(ISD::SRL, SDLoc(N), VT, SGN,
2036 SDValue ADD = DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, SRL);
2039 SDValue SRA = DAG.getNode(ISD::SRA, SDLoc(N), VT, ADD,
2048 return DAG.getNode(ISD::SUB, SDLoc(N), VT, DAG.getConstant(0, VT), SRA);
2059 if (N0.getOpcode() == ISD::UNDEF)
2062 if (N1.getOpcode() == ISD::UNDEF)
2083 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C);
2086 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0,
2090 if (N1.getOpcode() == ISD::SHL) {
2094 SDValue Add = DAG.getNode(ISD::ADD, SDLoc(N), ADDVT,
2100 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0, Add);
2111 if (N0.getOpcode() == ISD::UNDEF)
2114 if (N1.getOpcode() == ISD::UNDEF)
2129 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C);
2134 return DAG.getNode(ISD::UREM, SDLoc(N), VT, N0, N1);
2140 SDValue Div = DAG.getNode(ISD::SDIV, SDLoc(N), VT, N0, N1);
2144 SDValue Mul = DAG.getNode(ISD::MUL, SDLoc(N), VT,
2146 SDValue Sub = DAG.getNode(ISD::SUB, SDLoc(N), VT, N0, Mul);
2153 if (N0.getOpcode() == ISD::UNDEF)
2156 if (N1.getOpcode() == ISD::UNDEF)
2171 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C);
2174 return DAG.getNode(ISD::AND, SDLoc(N), VT, N0,
2177 if (N1.getOpcode() == ISD::SHL) {
2181 DAG.getNode(ISD::ADD, SDLoc(N), VT, N1,
2185 return DAG.getNode(ISD::AND, SDLoc(N), VT, N0, Add);
2193 SDValue Div = DAG.getNode(ISD::UDIV, SDLoc(N), VT, N0, N1);
2197 SDValue Mul = DAG.getNode(ISD::MUL, SDLoc(N), VT,
2199 SDValue Sub = DAG.getNode(ISD::SUB, SDLoc(N), VT, N0, Mul);
2206 if (N0.getOpcode() == ISD::UNDEF)
2209 if (N1.getOpcode() == ISD::UNDEF)
2227 return DAG.getNode(ISD::SRA, SDLoc(N), N0.getValueType(), N0,
2231 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2240 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2241 N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0);
2242 N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1);
2243 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
2244 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
2246 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1);
2267 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2276 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2277 N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0);
2278 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N1);
2279 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
2280 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
2282 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1);
2346 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS);
2358 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2359 SDValue Lo = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(0));
2360 SDValue Hi = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(1));
2361 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi);
2363 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
2365 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi);
2367 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo);
2376 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU);
2388 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2389 SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(0));
2390 SDValue Hi = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(1));
2391 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi);
2393 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
2395 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi);
2397 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo);
2409 return DAG.getNode(ISD::SADDO, SDLoc(N), N->getVTList(),
2419 return DAG.getNode(ISD::UADDO, SDLoc(N), N->getVTList(),
2426 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM);
2433 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM);
2458 if ((N0.getOpcode() == ISD::ZERO_EXTEND ||
2459 N0.getOpcode() == ISD::SIGN_EXTEND ||
2461 (N0.getOpcode() == ISD::ANY_EXTEND &&
2463 (N0.getOpcode() == ISD::TRUNCATE &&
2481 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
2482 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) &&
2499 if ((N0.getOpcode() == ISD::BITCAST ||
2500 N0.getOpcode() == ISD::SCALAR_TO_VECTOR) &&
2529 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG) {
2546 if (N->getOpcode() == ISD::XOR && ShOp.getOpcode() != ISD::UNDEF) {
2567 if (N->getOpcode() == ISD::XOR && ShOp.getOpcode() != ISD::UNDEF) {
2605 if (ISD::isBuildVectorAllZeros(N0.getNode()))
2607 if (ISD::isBuildVectorAllZeros(N1.getNode()))
2611 if (ISD::isBuildVectorAllOnes(N0.getNode()))
2613 if (ISD::isBuildVectorAllOnes(N1.getNode()))
2618 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2622 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C);
2625 return DAG.getNode(ISD::AND, SDLoc(N), VT, N1, N0);
2634 SDValue RAND = ReassociateOps(ISD::AND, SDLoc(N), N0, N1);
2638 if (N1C && N0.getOpcode() == ISD::OR)
2643 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
2648 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N),
2667 if ((N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
2668 N0.getOperand(0).getOpcode() == ISD::LOAD) ||
2669 N0.getOpcode() == ISD::LOAD) {
2670 LoadSDNode *Load = cast<LoadSDNode>( (N0.getOpcode() == ISD::LOAD) ?
2715 bool CanZextLoadProfitably = TLI.isLoadExtLegal(ISD::ZEXTLOAD,
2727 case ISD::EXTLOAD: B = CanZextLoadProfitably; break;
2728 case ISD::ZEXTLOAD:
2729 case ISD::NON_EXTLOAD: B = true; break;
2736 if (Load->getExtensionType() == ISD::EXTLOAD) {
2737 NewLoad = DAG.getLoad(Load->getAddressingMode(), ISD::ZEXTLOAD,
2762 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
2763 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
2768 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) {
2769 SDValue ORNode = DAG.getNode(ISD::OR, SDLoc(N0),
2775 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
2776 SDValue ANDNode = DAG.getNode(ISD::AND, SDLoc(N0),
2782 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
2783 SDValue ORNode = DAG.getNode(ISD::OR, SDLoc(N0),
2792 Op0 == ISD::SETNE && ((cast<ConstantSDNode>(LR)->isNullValue() &&
2796 SDValue ADDNode = DAG.getNode(ISD::ADD, SDLoc(N0), LL.getValueType(),
2800 DAG.getConstant(2, LL.getValueType()), ISD::SETUGE);
2804 Op1 = ISD::getSetCCSwappedOperands(Op1);
2809 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
2810 if (Result != ISD::SETCC_INVALID &&
2813 TLI.isOperationLegal(ISD::SETCC,
2833 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) {
2842 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) {
2843 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N0), VT,
2852 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
2862 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) {
2863 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N0), VT,
2875 if (N1C && (N0.getOpcode() == ISD::LOAD ||
2876 (N0.getOpcode() == ISD::ANY_EXTEND &&
2877 N0.getOperand(0).getOpcode() == ISD::LOAD))) {
2878 bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND;
2882 if (LN0->getExtensionType() != ISD::SEXTLOAD &&
2890 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) {
2894 DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(LN0), LoadResultTy,
2906 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) {
2919 NewPtr = DAG.getNode(ISD::ADD, SDLoc(LN0), PtrType,
2928 DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(LN0), LoadResultTy,
2941 if (N0.getOpcode() == ISD::ADD && N1.getOpcode() == ISD::SRL &&
2957 DAG.getNode(ISD::ADD, SDLoc(N0), VT,
2969 if (N1C && N1C->getAPIntValue() == 0xffff && N0.getOpcode() == ISD::OR) {
2989 if (!TLI.isOperationLegal(ISD::BSWAP, VT))
2995 if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL)
2997 if (N1.getOpcode() == ISD::AND && N1.getOperand(0).getOpcode() == ISD::SHL)
2999 if (N0.getOpcode() == ISD::AND) {
3009 if (N1.getOpcode() == ISD::AND) {
3019 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
3021 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
3036 if (!LookPassAnd0 && N00.getOpcode() == ISD::AND) {
3047 if (!LookPassAnd1 && N10.getOpcode() == ISD::AND) {
3078 SDValue Res = DAG.getNode(ISD::BSWAP, SDLoc(N), VT, N00);
3080 Res = DAG.getNode(ISD::SRL, SDLoc(N), VT, Res,
3093 if (Opc != ISD::AND && Opc != ISD::SHL && Opc != ISD::SRL)
3112 if (Opc == ISD::AND) {
3116 if (N0.getOpcode() != ISD::SRL)
3124 if (N0.getOpcode() != ISD::SHL)
3130 } else if (Opc == ISD::SHL) {
3138 } else { // Opc == ISD::SRL
3165 if (!TLI.isOperationLegal(ISD::BSWAP, VT))
3172 if (N0.getOpcode() != ISD::OR)
3177 if (N1.getOpcode() == ISD::OR &&
3199 if (N00.getOpcode() != ISD::OR)
3213 SDValue BSwap = DAG.getNode(ISD::BSWAP, SDLoc(N), VT,
3219 if (TLI.isOperationLegalOrCustom(ISD::ROTL, VT))
3220 return DAG.getNode(ISD::ROTL, SDLoc(N), VT, BSwap, ShAmt);
3221 if (TLI.isOperationLegalOrCustom(ISD::ROTR, VT))
3222 return DAG.getNode(ISD::ROTR, SDLoc(N), VT, BSwap, ShAmt);
3223 return DAG.getNode(ISD::OR, SDLoc(N), VT,
3224 DAG.getNode(ISD::SHL, SDLoc(N), VT, BSwap, ShAmt),
3225 DAG.getNode(ISD::SRL, SDLoc(N), VT, BSwap, ShAmt));
3242 if (ISD::isBuildVectorAllZeros(N0.getNode()))
3244 if (ISD::isBuildVectorAllZeros(N1.getNode()))
3248 if (ISD::isBuildVectorAllOnes(N0.getNode()))
3250 if (ISD::isBuildVectorAllOnes(N1.getNode()))
3259 ISD::isBuildVectorAllZeros(N0.getOperand(1).getNode())) {
3310 (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)) {
3316 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C);
3319 return DAG.getNode(ISD::OR, SDLoc(N), VT, N1, N0);
3339 SDValue ROR = ReassociateOps(ISD::OR, SDLoc(N), N0, N1);
3344 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
3348 SDValue COR = DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1);
3351 return DAG.getNode(ISD::AND, SDLoc(N), VT,
3352 DAG.getNode(ISD::OR, SDLoc(N0), VT,
3358 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
3359 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
3366 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
3367 SDValue ORNode = DAG.getNode(ISD::OR, SDLoc(LR),
3375 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
3376 SDValue ANDNode = DAG.getNode(ISD::AND, SDLoc(LR),
3384 Op1 = ISD::getSetCCSwappedOperands(Op1);
3389 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
3390 if (Result != ISD::SETCC_INVALID &&
3393 TLI.isOperationLegal(ISD::SETCC,
3407 if (N0.getOpcode() == ISD::AND &&
3408 N1.getOpcode() == ISD::AND &&
3409 N0.getOperand(1).getOpcode() == ISD::Constant &&
3410 N1.getOperand(1).getOpcode() == ISD::Constant &&
3422 SDValue X = DAG.getNode(ISD::OR, SDLoc(N0), VT,
3424 return DAG.getNode(ISD::AND, SDLoc(N), VT, X,
3443 if (Op.getOpcode() == ISD::AND) {
3452 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
3502 if (Neg.getOpcode() == ISD::AND &&
3504 Neg.getOperand(1).getOpcode() == ISD::Constant &&
3511 if (Neg.getOpcode() != ISD::SUB)
3521 Pos.getOpcode() == ISD::AND &&
3522 Pos.getOperand(1).getOpcode() == ISD::Constant &&
3547 else if (Pos.getOpcode() == ISD::ADD &&
3549 Pos.getOperand(1).getOpcode() == ISD::Constant)
3597 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT);
3598 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT);
3619 if (RHSShift.getOpcode() == ISD::SHL) {
3633 if (LHSShiftAmt.getOpcode() == ISD::Constant &&
3634 RHSShiftAmt.getOpcode() == ISD::Constant) {
3640 SDValue Rot = DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT,
3656 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT));
3670 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND ||
3671 LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND ||
3672 LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND ||
3673 LHSShiftAmt.getOpcode() == ISD::TRUNCATE) &&
3674 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND ||
3675 RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND ||
3676 RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND ||
3677 RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) {
3683 LExtOp0, RExtOp0, ISD::ROTL, ISD::ROTR, DL);
3688 RExtOp0, LExtOp0, ISD::ROTR, ISD::ROTL, DL);
3709 if (ISD::isBuildVectorAllZeros(N0.getNode()))
3711 if (ISD::isBuildVectorAllZeros(N1.getNode()))
3716 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF)
3719 if (N0.getOpcode() == ISD::UNDEF)
3721 if (N1.getOpcode() == ISD::UNDEF)
3725 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C);
3728 return DAG.getNode(ISD::XOR, SDLoc(N), VT, N1, N0);
3733 SDValue RXOR = ReassociateOps(ISD::XOR, SDLoc(N), N0, N1);
3740 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
3748 case ISD::SETCC:
3750 case ISD::SELECT_CC:
3758 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND &&
3762 V = DAG.getNode(ISD::XOR, SDLoc(N0), V.getValueType(), V,
3765 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT, V);
3770 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
3773 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
3774 LHS = DAG.getNode(ISD::XOR, SDLoc(LHS), VT, LHS, N1); // LHS = ~LHS
3775 RHS = DAG.getNode(ISD::XOR, SDLoc(RHS), VT, RHS, N1); // RHS = ~RHS
3782 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
3785 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
3786 LHS = DAG.getNode(ISD::XOR, SDLoc(LHS), VT, LHS, N1); // LHS = ~LHS
3787 RHS = DAG.getNode(ISD::XOR, SDLoc(RHS), VT, RHS, N1); // RHS = ~RHS
3793 if (N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
3798 return DAG.getNode(ISD::AND, SDLoc(N), VT, NotX, N1);
3801 if (N1C && N0.getOpcode() == ISD::XOR) {
3805 return DAG.getNode(ISD::XOR, SDLoc(N), VT, N0.getOperand(1),
3809 ISD::XOR, SDLoc(N), VT, N0.getOperand(0),
3849 case ISD::OR:
3850 case ISD::XOR:
3853 case ISD::AND:
3856 case ISD::ADD:
3857 if (N->getOpcode() != ISD::SHL)
3873 if ((BinOpLHSVal->getOpcode() != ISD::SHL &&
3874 BinOpLHSVal->getOpcode() != ISD::SRA &&
3875 BinOpLHSVal->getOpcode() != ISD::SRL) ||
3885 if (N->getOpcode() == ISD::SRA) {
3910 assert(N->getOpcode() == ISD::TRUNCATE);
3911 assert(N->getOperand(0).getOpcode() == ISD::AND);
3923 return DAG.getNode(ISD::AND, SDLoc(N), TruncVT,
3924 DAG.getNode(ISD::TRUNCATE, SDLoc(N), TruncVT, N00),
3934 if (N->getOperand(1).getOpcode() == ISD::TRUNCATE &&
3935 N->getOperand(1).getOperand(0).getOpcode() == ISD::AND) {
3961 if (N0.getOpcode() == ISD::AND) {
3966 if (N01CV && N01CV->isConstant() && N00.getOpcode() == ISD::SETCC &&
3969 SDValue C = DAG.FoldConstantArithmetic(ISD::SHL, VT, N01CV, N1CV);
3971 return DAG.getNode(ISD::AND, SDLoc(N), VT, N00, C);
3981 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C);
3992 if (N0.getOpcode() == ISD::UNDEF)
3999 if (N1.getOpcode() == ISD::TRUNCATE &&
4000 N1.getOperand(0).getOpcode() == ISD::AND) {
4003 return DAG.getNode(ISD::SHL, SDLoc(N), VT, N0, NewOp1);
4010 if (N1C && N0.getOpcode() == ISD::SHL) {
4016 return DAG.getNode(ISD::SHL, SDLoc(N), VT, N0.getOperand(0),
4026 if (N1C && (N0.getOpcode() == ISD::ZERO_EXTEND ||
4027 N0.getOpcode() == ISD::ANY_EXTEND ||
4028 N0.getOpcode() == ISD::SIGN_EXTEND) &&
4029 N0.getOperand(0).getOpcode() == ISD::SHL) {
4039 return DAG.getNode(ISD::SHL, SDLoc(N0), VT,
4050 if (N1C && N0.getOpcode() == ISD::ZERO_EXTEND && N0.hasOneUse() &&
4051 N0.getOperand(0).getOpcode() == ISD::SRL) {
4060 SDValue NewSHL = DAG.getNode(ISD::SHL, SDLoc(N), NewOp0.getValueType(),
4063 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N0), VT, NewSHL);
4073 if (N1C && N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
4082 Shift = DAG.getNode(ISD::SHL, SDLoc(N), VT, N0.getOperand(0),
4086 Shift = DAG.getNode(ISD::SRL, SDLoc(N), VT, N0.getOperand(0),
4089 return DAG.getNode(ISD::AND, SDLoc(N0), VT, Shift,
4095 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) {
4100 return DAG.getNode(ISD::AND, SDLoc(N), VT, N0.getOperand(0),
4131 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C);
4146 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
4153 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, ExtVT)))
4154 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT,
4159 if (N1C && N0.getOpcode() == ISD::SRA) {
4164 return DAG.getNode(ISD::SRA, SDLoc(N), VT, N0.getOperand(0),
4174 if (N0.getOpcode() == ISD::SHL && N1C) {
4193 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) &&
4194 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) &&
4199 SDValue Shift = DAG.getNode(ISD::SRL, SDLoc(N0), VT,
4201 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SDLoc(N0), TruncVT,
4203 return DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N),
4210 if (N1.getOpcode() == ISD::TRUNCATE &&
4211 N1.getOperand(0).getOpcode() == ISD::AND) {
4214 return DAG.getNode(ISD::SRA, SDLoc(N), VT, N0, NewOp1);
4219 if (N0.getOpcode() == ISD::TRUNCATE &&
4220 (N0.getOperand(0).getOpcode() == ISD::SRL ||
4221 N0.getOperand(0).getOpcode() == ISD::SRA) &&
4234 SDValue SRA = DAG.getNode(ISD::SRA, SDLoc(N), LargeVT,
4236 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, SRA);
4248 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0, N1);
4277 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C);
4293 if (N1C && N0.getOpcode() == ISD::SRL) {
4299 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0.getOperand(0),
4305 if (N1C && N0.getOpcode() == ISD::TRUNCATE &&
4306 N0.getOperand(0).getOpcode() == ISD::SRL &&
4318 return DAG.getNode(ISD::TRUNCATE, SDLoc(N0), VT,
4319 DAG.getNode(ISD::SRL, SDLoc(N0), InnerShiftVT,
4326 if (N1C && N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1) {
4330 return DAG.getNode(ISD::AND, SDLoc(N), VT, N0.getOperand(0),
4336 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
4343 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) {
4345 SDValue SmallShift = DAG.getNode(ISD::SRL, SDLoc(N0), SmallVT,
4350 return DAG.getNode(ISD::AND, SDLoc(N), VT,
4351 DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), VT, SmallShift),
4359 if (N0.getOpcode() == ISD::SRA)
4360 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0.getOperand(0), N1);
4364 if (N1C && N0.getOpcode() == ISD::CTLZ &&
4388 Op = DAG.getNode(ISD::SRL, SDLoc(N0), VT, Op,
4393 return DAG.getNode(ISD::XOR, SDLoc(N), VT,
4399 if (N1.getOpcode() == ISD::TRUNCATE &&
4400 N1.getOperand(0).getOpcode() == ISD::AND) {
4403 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0, NewOp1);
4441 if (Use->getOpcode() == ISD::BRCOND)
4443 else if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse()) {
4446 if (Use->getOpcode() == ISD::BRCOND)
4460 return DAG.getNode(ISD::CTLZ, SDLoc(N), VT, N0);
4470 return DAG.getNode(ISD::CTLZ_ZERO_UNDEF, SDLoc(N), VT, N0);
4480 return DAG.getNode(ISD::CTTZ, SDLoc(N), VT, N0);
4490 return DAG.getNode(ISD::CTTZ_ZERO_UNDEF, SDLoc(N), VT, N0);
4500 return DAG.getNode(ISD::CTPOP, SDLoc(N), VT, N0);
4525 return DAG.getNode(ISD::OR, SDLoc(N), VT, N0, N2);
4544 return DAG.getNode(ISD::XOR, SDLoc(N), VT0,
4546 XORNode = DAG.getNode(ISD::XOR, SDLoc(N0), VT0,
4550 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT, XORNode);
4551 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, XORNode);
4557 return DAG.getNode(ISD::AND, SDLoc(N), VT, NOTNode, N2);
4563 return DAG.getNode(ISD::OR, SDLoc(N), VT, NOTNode, N1);
4567 return DAG.getNode(ISD::AND, SDLoc(N), VT, N0, N1);
4571 return DAG.getNode(ISD::OR, SDLoc(N), VT, N0, N2);
4575 return DAG.getNode(ISD::AND, SDLoc(N), VT, N0, N1);
4582 if (N0.getOpcode() == ISD::SETCC) {
4584 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT)) ||
4585 TLI.isOperationLegal(ISD::SELECT_CC, VT))
4586 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), VT,
4621 assert(LHS.getOpcode() == ISD::CONCAT_VECTORS &&
4622 RHS.getOpcode() == ISD::CONCAT_VECTORS &&
4623 Cond.getOpcode() == ISD::BUILD_VECTOR);
4632 if (Cond->getOperand(i)->getOpcode() == ISD::UNDEF)
4644 if (Cond->getOperand(i)->getOpcode() == ISD::UNDEF)
4657 ISD::CONCAT_VECTORS, dl, VT,
4673 if (N0.getOpcode() == ISD::SETCC) {
4675 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
4677 bool RHSIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
4679 if (((RHSIsAllZeros && (CC == ISD::SETGT || CC == ISD::SETGE)) ||
4680 (ISD::isBuildVectorAllOnes(RHS.getNode()) && CC == ISD::SETGT)) &&
4681 N1 == LHS && N2.getOpcode() == ISD::SUB && N1 == N2.getOperand(1))
4682 isAbs = ISD::isBuildVectorAllZeros(N2.getOperand(0).getNode());
4683 else if ((RHSIsAllZeros && (CC == ISD::SETLT || CC == ISD::SETLE)) &&
4684 N2 == LHS && N1.getOpcode() == ISD::SUB && N2 == N1.getOperand(1))
4685 isAbs = ISD::isBuildVectorAllZeros(N1.getOperand(0).getNode());
4690 ISD::SRA, DL, VT, LHS,
4692 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, LHS, Shift);
4695 return DAG.getNode(ISD::XOR, DL, VT, Add, Shift);
4703 if (N0.getOpcode() == ISD::SETCC) {
4724 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
4728 if (ISD::isBuildVectorAllOnes(N0.getNode()))
4731 if (ISD::isBuildVectorAllZeros(N0.getNode()))
4737 if (N1.getOpcode() == ISD::CONCAT_VECTORS &&
4738 N2.getOpcode() == ISD::CONCAT_VECTORS &&
4739 ISD::isBuildVectorOfConstantSDNodes(N0.getNode())) {
4754 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
4774 if (SCC.getOpcode() == ISD::SETCC)
4775 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), N2.getValueType(),
4807 assert((Opcode == ISD::SIGN_EXTEND || Opcode == ISD::ZERO_EXTEND ||
4808 Opcode == ISD::ANY_EXTEND) && "Expected EXTEND dag node in input!");
4822 ISD::isBuildVectorOfConstantSDNodes(N0.getNode())))
4835 if (Op->getOpcode() == ISD::UNDEF) {
4842 if (Opcode == ISD::SIGN_EXTEND)
4850 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Elts).getNode();
4872 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) {
4873 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get();
4874 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC))
4895 if (User->getOpcode() == ISD::CopyToReg)
4904 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) {
4919 ISD::NodeType ExtType) {
4934 CombineTo(SetCC, DAG.getNode(ISD::SETCC, DL, SetCC->getValueType(0), Ops));
4948 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
4949 return DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N), VT,
4952 if (N0.getOpcode() == ISD::TRUNCATE) {
4983 return DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N), VT, Op);
4988 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, Op);
4992 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG,
4995 Op = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N0), VT, Op);
4997 Op = DAG.getNode(ISD::TRUNCATE, SDLoc(N0), VT, Op);
4998 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT, Op,
5007 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
5008 ISD::isUNINDEXEDLoad(N0.getNode()) &&
5010 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) {
5014 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI);
5017 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, SDLoc(N), VT,
5022 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SDLoc(N0),
5026 ISD::SIGN_EXTEND);
5033 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
5034 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
5038 TLI.isLoadExtLegal(ISD::SEXTLOAD, MemVT)) {
5039 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, SDLoc(N), VT,
5045 DAG.getNode(ISD::TRUNCATE, SDLoc(N0),
5054 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR ||
5055 N0.getOpcode() == ISD::XOR) &&
5057 N0.getOperand(1).getOpcode() == ISD::Constant &&
5058 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()) &&
5061 if (LN0->getExtensionType() != ISD::ZEXTLOAD && LN0->isUnindexed()) {
5065 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::SIGN_EXTEND,
5068 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, SDLoc(LN0), VT,
5076 SDValue Trunc = DAG.getNode(ISD::TRUNCATE,
5082 ISD::SIGN_EXTEND);
5088 if (N0.getOpcode() == ISD::SETCC) {
5134 if (!LegalOperations || TLI.isOperationLegal(ISD::SETCC, SetCCVT)) {
5136 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
5150 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) &&
5152 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT, N0);
5164 if (N->getOpcode() == ISD::TRUNCATE) {
5170 if (N->getOpcode() != ISD::SETCC || N->getValueType(0) != MVT::i1 ||
5171 cast<CondCodeSDNode>(N->getOperand(2))->get() != ISD::SETNE)
5205 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
5206 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT,
5225 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT, Op);
5227 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, Op);
5235 if (N0.getOpcode() == ISD::TRUNCATE) {
5249 if (N0.getOpcode() == ISD::TRUNCATE &&
5250 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) {
5267 Op = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), VT, Op);
5270 Op = DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, Op);
5279 if (N0.getOpcode() == ISD::AND &&
5280 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
5281 N0.getOperand(1).getOpcode() == ISD::Constant &&
5287 X = DAG.getNode(ISD::ANY_EXTEND, SDLoc(X), VT, X);
5289 X = DAG.getNode(ISD::TRUNCATE, SDLoc(X), VT, X);
5293 return DAG.getNode(ISD::AND, SDLoc(N), VT,
5301 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
5302 ISD::isUNINDEXEDLoad(N0.getNode()) &&
5304 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) {
5308 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI);
5311 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N), VT,
5316 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SDLoc(N0),
5321 ISD::ZERO_EXTEND);
5328 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR ||
5329 N0.getOpcode() == ISD::XOR) &&
5331 N0.getOperand(1).getOpcode() == ISD::Constant &&
5332 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()) &&
5335 if (LN0->getExtensionType() != ISD::SEXTLOAD && LN0->isUnindexed()) {
5339 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::ZERO_EXTEND,
5342 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(LN0), VT,
5350 SDValue Trunc = DAG.getNode(ISD::TRUNCATE,
5356 ISD::ZERO_EXTEND);
5364 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
5365 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
5369 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT)) {
5370 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N), VT,
5376 DAG.getNode(ISD::TRUNCATE, SDLoc(N0), N0.getValueType(),
5383 if (N0.getOpcode() == ISD::SETCC) {
5401 return DAG.getNode(ISD::AND, SDLoc(N), VT,
5405 DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), VT,
5421 return DAG.getNode(ISD::AND, SDLoc(N), VT,
5423 DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), VT, OneOps));
5435 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) &&
5437 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND &&
5441 if (N0.getOpcode() == ISD::SHL) {
5455 ShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, ShAmt);
5458 DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)),
5476 if (N0.getOpcode() == ISD::ANY_EXTEND ||
5477 N0.getOpcode() == ISD::ZERO_EXTEND ||
5478 N0.getOpcode() == ISD::SIGN_EXTEND)
5483 if (N0.getOpcode() == ISD::TRUNCATE) {
5497 if (N0.getOpcode() == ISD::TRUNCATE) {
5502 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, TruncOp);
5503 return DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), VT, TruncOp);
5508 if (N0.getOpcode() == ISD::AND &&
5509 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
5510 N0.getOperand(1).getOpcode() == ISD::Constant &&
5515 X = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), VT, X);
5517 X = DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, X);
5521 return DAG.getNode(ISD::AND, SDLoc(N), VT,
5529 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
5530 ISD::isUNINDEXEDLoad(N0.getNode()) &&
5532 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) {
5536 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI);
5539 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, SDLoc(N), VT,
5544 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SDLoc(N0),
5548 ISD::ANY_EXTEND);
5556 if (N0.getOpcode() == ISD::LOAD &&
5557 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
5560 ISD::LoadExtType ExtType = LN0->getExtensionType();
5568 DAG.getNode(ISD::TRUNCATE, SDLoc(N0),
5575 if (N0.getOpcode() == ISD::SETCC) {
5623 case ISD::Constant: {
5632 case ISD::OR:
5633 case ISD::XOR:
5640 case ISD::SRL:
5653 return DAG.getNode(ISD::SRL, SDLoc(V), V.getValueType(),
5668 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
5679 if (Opc == ISD::SIGN_EXTEND_INREG) {
5680 ExtType = ISD::SEXTLOAD;
5682 } else if (Opc == ISD::SRL) {
5684 ExtType = ISD::ZEXTLOAD;
5702 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
5719 if (cast<LoadSDNode>(N0)->getExtensionType() == ISD::SEXTLOAD)
5733 if (ShAmt == 0 && N0.getOpcode() == ISD::SHL && N0.hasOneUse() &&
5766 if (LN0->getExtensionType() != ISD::NON_EXTLOAD &&
5786 SDValue NewPtr = DAG.getNode(ISD::ADD, SDLoc(LN0),
5792 if (ExtType == ISD::NON_EXTLOAD)
5820 Result = DAG.getNode(ISD::SHL, SDLoc(N0), VT,
5837 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF)
5838 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT, N0, N1);
5845 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
5847 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT,
5853 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) {
5856 (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND, VT)))
5857 return DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N), VT, N00, N1);
5878 if (N0.getOpcode() == ISD::SRL) {
5885 return DAG.getNode(ISD::SRA, SDLoc(N), VT,
5891 if (ISD::isEXTLoad(N0.getNode()) &&
5892 ISD::isUNINDEXEDLoad(N0.getNode()) &&
5895 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) {
5897 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, SDLoc(N), VT,
5907 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
5911 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) {
5913 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, SDLoc(N), VT,
5923 if (EVTBits <= 16 && N0.getOpcode() == ISD::OR) {
5927 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT,
5933 if (ISD::isBuildVectorOfConstantSDNodes(N0.getNode())) {
5940 if (Op->getOpcode() == ISD::UNDEF) {
5951 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), VT, Elts);
5967 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, N0);
5969 if (N0.getOpcode() == ISD::TRUNCATE)
5970 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, N0.getOperand(0));
5972 if (N0.getOpcode() == ISD::ZERO_EXTEND ||
5973 N0.getOpcode() == ISD::SIGN_EXTEND ||
5974 N0.getOpcode() == ISD::ANY_EXTEND) {
5981 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, N0.getOperand(0));
5997 if (N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6016 SDValue V = DAG.getNode(ISD::BITCAST, SDLoc(N),
6019 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
6030 N0.getOpcode() == ISD::BITCAST && N0.hasOneUse() &&
6031 N0.getOperand(0).getOpcode() == ISD::BUILD_VECTOR &&
6052 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), VT, Opnds);
6066 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, Shorter);
6076 if (N0.hasOneUse() && ISD::isUNINDEXEDLoad(N0.getNode())) {
6091 if (N0.getOpcode() == ISD::CONCAT_VECTORS && !LegalTypes) {
6099 if (X.getOpcode() != ISD::UNDEF) {
6123 SDValue NV = DAG.getNode(ISD::TRUNCATE, SDLoc(V), VTs[i], V);
6127 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT, Opnds);
6141 if (Elt.getOpcode() != ISD::MERGE_VALUES)
6149 assert(N->getOpcode() == ISD::BUILD_PAIR);
6153 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse() ||
6158 if (ISD::isNON_EXTLoad(LD2) &&
6170 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT)))
6188 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() &&
6201 SDValue Res = DAG.getNode(ISD::BITCAST, SDLoc(N), VT, N0);
6217 if (N0.getOpcode() == ISD::BITCAST)
6218 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT,
6223 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
6229 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT)) &&
6244 DAG.getNode(ISD::BITCAST, SDLoc(N0),
6254 if (((N0.getOpcode() == ISD::FNEG && !TLI.isFNegFree(N0.getValueType())) ||
6255 (N0.getOpcode() == ISD::FABS && !TLI.isFAbsFree(N0.getValueType()))) &&
6258 SDValue NewConv = DAG.getNode(ISD::BITCAST, SDLoc(N0), VT,
6263 if (N0.getOpcode() == ISD::FNEG)
6264 return DAG.getNode(ISD::XOR, SDLoc(N), VT,
6266 assert(N0.getOpcode() == ISD::FABS);
6267 return DAG.getNode(ISD::AND, SDLoc(N), VT,
6275 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() &&
6281 SDValue X = DAG.getNode(ISD::BITCAST, SDLoc(N0),
6288 X = DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N), VT, X);
6293 X = DAG.getNode(ISD::SRL, SDLoc(X),
6297 X = DAG.getNode(ISD::TRUNCATE, SDLoc(X), VT, X);
6302 X = DAG.getNode(ISD::AND, SDLoc(X), VT,
6306 SDValue Cst = DAG.getNode(ISD::BITCAST, SDLoc(N0),
6308 Cst = DAG.getNode(ISD::AND, SDLoc(Cst), VT,
6312 return DAG.getNode(ISD::OR, SDLoc(N), VT, X, Cst);
6317 if (N0.getOpcode() == ISD::BUILD_PAIR) {
6352 if (BV->getOpcode() == ISD::SCALAR_TO_VECTOR)
6353 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(BV), VT,
6354 DAG.getNode(ISD::BITCAST, SDLoc(BV),
6363 Op = DAG.getNode(ISD::TRUNCATE, SDLoc(BV), SrcEltVT, Op);
6364 Ops.push_back(DAG.getNode(ISD::BITCAST, SDLoc(BV),
6368 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(BV), VT, Ops);
6410 if (Op.getOpcode() == ISD::UNDEF) continue;
6424 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(BV), VT, Ops);
6429 bool isS2V = ISD::isScalarToVector(BV);
6436 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) {
6450 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(BV), VT,
6460 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(BV), VT, Ops);
6478 return DAG.getNode(ISD::FADD, SDLoc(N), VT, N0, N1);
6481 return DAG.getNode(ISD::FADD, SDLoc(N), VT, N1, N0);
6487 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) &&
6489 return DAG.getNode(ISD::FSUB, SDLoc(N), VT, N0,
6492 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) &&
6494 return DAG.getNode(ISD::FSUB, SDLoc(N), VT, N1,
6499 N0.getOpcode() == ISD::FADD && N0.getNode()->hasOneUse() &&
6501 return DAG.getNode(ISD::FADD, SDLoc(N), VT, N0.getOperand(0),
6502 DAG.getNode(ISD::FADD, SDLoc(N), VT,
6518 N0.getOpcode() == ISD::FNEG && N0.getOperand(0) == N1)
6523 N1.getOpcode() == ISD::FNEG && N1.getOperand(0) == N0)
6530 TLI.isOperationLegalOrCustom(ISD::FMUL, VT) &&
6532 if (N0.getOpcode() == ISD::FMUL) {
6538 SDValue NewCFP = DAG.getNode(ISD::FADD, SDLoc(N), VT,
6541 return DAG.getNode(ISD::FMUL, SDLoc(N), VT,
6547 SDValue NewCFP = DAG.getNode(ISD::FADD, SDLoc(N), VT,
6550 return DAG.getNode(ISD::FMUL, SDLoc(N), VT,
6555 if (CFP00 && !CFP01 && N1.getOpcode() == ISD::FADD &&
6558 SDValue NewCFP = DAG.getNode(ISD::FADD, SDLoc(N), VT,
6561 return DAG.getNode(ISD::FMUL, SDLoc(N), VT,
6566 if (CFP01 && !CFP00 && N1.getOpcode() == ISD::FADD &&
6569 SDValue NewCFP = DAG.getNode(ISD::FADD, SDLoc(N), VT,
6572 return DAG.getNode(ISD::FMUL, SDLoc(N), VT,
6577 if (N1.getOpcode() == ISD::FMUL) {
6583 SDValue NewCFP = DAG.getNode(ISD::FADD, SDLoc(N), VT,
6586 return DAG.getNode(ISD::FMUL, SDLoc(N), VT,
6592 SDValue NewCFP = DAG.getNode(ISD::FADD, SDLoc(N), VT,
6595 return DAG.getNode(ISD::FMUL, SDLoc(N), VT,
6601 if (CFP10 && !CFP11 && N0.getOpcode() == ISD::FADD &&
6604 SDValue NewCFP = DAG.getNode(ISD::FADD, SDLoc(N), VT,
6607 return DAG.getNode(ISD::FMUL, SDLoc(N), VT,
6612 if (CFP11 && !CFP10 && N0.getOpcode() == ISD::FADD &&
6615 SDValue NewCFP = DAG.getNode(ISD::FADD, SDLoc(N), VT,
6618 return DAG.getNode(ISD::FMUL, SDLoc(N), VT,
6623 if (N0.getOpcode() == ISD::FADD && AllowNewFpConst) {
6628 return DAG.getNode(ISD::FMUL, SDLoc(N), VT,
6632 if (N1.getOpcode() == ISD::FADD && AllowNewFpConst) {
6637 return DAG.getNode(ISD::FMUL, SDLoc(N), VT,
6643 N0.getOpcode() == ISD::FADD && N1.getOpcode() == ISD::FADD &&
6647 return DAG.getNode(ISD::FMUL, SDLoc(N), VT,
6656 (!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FMA, VT))) {
6659 if (N0.getOpcode() == ISD::FMUL && N0->hasOneUse())
6660 return DAG.getNode(ISD::FMA, SDLoc(N), VT,
6665 if (N1.getOpcode() == ISD::FMUL && N1->hasOneUse())
6666 return DAG.getNode(ISD::FMA, SDLoc(N), VT,
6689 return DAG.getNode(ISD::FSUB, SDLoc(N), VT, N0, N1);
6699 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
6700 return DAG.getNode(ISD::FNEG, dl, VT, N1);
6704 return DAG.getNode(ISD::FADD, dl, VT, N0,
6715 if (N1.getOpcode() == ISD::FADD) {
6733 (!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FMA, VT))) {
6736 if (N0.getOpcode() == ISD::FMUL && N0->hasOneUse())
6737 return DAG.getNode(ISD::FMA, dl, VT,
6739 DAG.getNode(ISD::FNEG, dl, VT, N1));
6743 if (N1.getOpcode() == ISD::FMUL && N1->hasOneUse())
6744 return DAG.getNode(ISD::FMA, dl, VT,
6745 DAG.getNode(ISD::FNEG, dl, VT,
6750 if (N0.getOpcode() == ISD::FNEG &&
6751 N0.getOperand(0).getOpcode() == ISD::FMUL &&
6755 return DAG.getNode(ISD::FMA, dl, VT,
6756 DAG.getNode(ISD::FNEG, dl, VT, N00), N01,
6757 DAG.getNode(ISD::FNEG, dl, VT, N1));
6780 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, N0, N1);
6783 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, N1, N0);
6790 ISD::isBuildVectorAllZeros(N1.getNode()))
6797 return DAG.getNode(ISD::FADD, SDLoc(N), VT, N0, N0);
6800 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
6801 return DAG.getNode(ISD::FNEG, SDLoc(N), VT, N0);
6811 return DAG.getNode(ISD::FMUL, SDLoc(N), VT,
6819 N1CFP && N0.getOpcode() == ISD::FMUL &&
6821 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, N0.getOperand(0),
6822 DAG.getNode(ISD::FMUL, SDLoc(N), VT,
6844 return DAG.getNode(ISD::FADD, SDLoc(N), VT, N1, N2);
6846 return DAG.getNode(ISD::FADD, SDLoc(N), VT, N0, N2);
6850 return DAG.getNode(ISD::FMA, SDLoc(N), VT, N1, N0, N2);
6854 N2.getOpcode() == ISD::FMUL &&
6856 N2.getOperand(1).getOpcode() == ISD::ConstantFP) {
6857 return DAG.getNode(ISD::FMUL, dl, VT, N0,
6858 DAG.getNode(ISD::FADD, dl, VT, N1, N2.getOperand(1)));
6864 N0.getOpcode() == ISD::FMUL && N1CFP &&
6865 N0.getOperand(1).getOpcode() == ISD::ConstantFP) {
6866 return DAG.getNode(ISD::FMA, dl, VT,
6868 DAG.getNode(ISD::FMUL, dl, VT, N1, N0.getOperand(1)),
6876 return DAG.getNode(ISD::FADD, dl, VT, N0, N2);
6879 (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))) {
6880 SDValue RHSNeg = DAG.getNode(ISD::FNEG, dl, VT, N0);
6882 return DAG.getNode(ISD::FADD, dl, VT, N2, RHSNeg);
6888 return DAG.getNode(ISD::FMUL, dl, VT, N0,
6889 DAG.getNode(ISD::FADD, dl, VT,
6894 N2.getOpcode() == ISD::FNEG && N2.getOperand(0) == N0)
6895 return DAG.getNode(ISD::FMUL, dl, VT, N0,
6896 DAG.getNode(ISD::FADD, dl, VT,
6919 return DAG.getNode(ISD::FDIV, SDLoc(N), VT, N0, N1);
6933 // TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT) ||
6934 TLI.isOperationLegal(llvm::ISD::ConstantFP, VT) ||
6936 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, N0,
6948 return DAG.getNode(ISD::FDIV, SDLoc(N), VT,
6966 return DAG.getNode(ISD::FREM, SDLoc(N), VT, N0, N1);
6979 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT, N0, N1);
6986 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT))
6987 return DAG.getNode(ISD::FABS, SDLoc(N), VT, N0);
6989 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
6990 return DAG.getNode(ISD::FNEG, SDLoc(N), VT,
6991 DAG.getNode(ISD::FABS, SDLoc(N0), VT, N0));
6998 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
6999 N0.getOpcode() == ISD::FCOPYSIGN)
7000 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT,
7004 if (N1.getOpcode() == ISD::FABS)
7005 return DAG.getNode(ISD::FABS, SDLoc(N), VT, N0);
7008 if (N1.getOpcode() == ISD::FCOPYSIGN)
7009 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT,
7014 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND)
7015 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT,
7031 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT)))
7032 return DAG.getNode(ISD::SINT_TO_FP, SDLoc(N), VT, N0);
7036 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) &&
7037 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) {
7040 return DAG.getNode(ISD::UINT_TO_FP, SDLoc(N), VT, N0);
7044 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT) || !LegalOperations) {
7046 if (N0.getOpcode() == ISD::SETCC && N0.getValueType() == MVT::i1 &&
7049 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) {
7054 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), VT, Ops);
7059 if (N0.getOpcode() == ISD::ZERO_EXTEND &&
7060 N0.getOperand(0).getOpcode() == ISD::SETCC &&!VT.isVector() &&
7062 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) {
7067 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), VT, Ops);
7084 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT)))
7085 return DAG.getNode(ISD::UINT_TO_FP, SDLoc(N), VT, N0);
7089 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) &&
7090 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) {
7093 return DAG.getNode(ISD::SINT_TO_FP, SDLoc(N), VT, N0);
7097 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT) || !LegalOperations) {
7100 if (N0.getOpcode() == ISD::SETCC && !VT.isVector() &&
7102 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) {
7107 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), VT, Ops);
7121 return DAG.getNode(ISD::FP_TO_SINT, SDLoc(N), VT, N0);
7133 return DAG.getNode(ISD::FP_TO_UINT, SDLoc(N), VT, N0);
7146 return DAG.getNode(ISD::FP_ROUND, SDLoc(N), VT, N0, N1);
7149 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
7153 if (N0.getOpcode() == ISD::FP_ROUND) {
7157 return DAG.getNode(ISD::FP_ROUND, SDLoc(N), VT, N0.getOperand(0),
7162 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) {
7163 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, SDLoc(N0), VT,
7166 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT,
7182 return DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT, Round);
7195 N->use_begin()->getOpcode() == ISD::FP_ROUND)
7200 return DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT, N0);
7204 if (N0.getOpcode() == ISD::FP_ROUND
7209 return DAG.getNode(ISD::FP_ROUND, SDLoc(N), VT,
7211 return DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT, In);
7215 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
7217 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) {
7219 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, SDLoc(N), VT,
7225 DAG.getNode(ISD::FP_ROUND, SDLoc(N0),
7249 if (!TLI.isFNegFree(VT) && N0.getOpcode() == ISD::BITCAST &&
7256 Int = DAG.getNode(ISD::XOR, SDLoc(N0), IntVT, Int,
7259 return DAG.getNode(ISD::BITCAST, SDLoc(N),
7265 if (N0.getOpcode() == ISD::FMUL) {
7272 TLI.isOperationLegal(ISD::ConstantFP, N->getValueType(0))))
7274 ISD::FMUL, SDLoc(N), VT, N0.getOperand(0),
7275 DAG.getNode(ISD::FNEG, SDLoc(N), VT, N0.getOperand(1)));
7289 return DAG.getNode(ISD::FCEIL, SDLoc(N), VT, N0);
7301 return DAG.getNode(ISD::FTRUNC, SDLoc(N), VT, N0);
7313 return DAG.getNode(ISD::FFLOOR, SDLoc(N), VT, N0);
7330 return DAG.getNode(ISD::FABS, SDLoc(N), VT, N0);
7332 if (N0.getOpcode() == ISD::FABS)
7336 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
7337 return DAG.getNode(ISD::FABS, SDLoc(N), VT, N0.getOperand(0));
7342 N0.getOpcode() == ISD::BITCAST && N0.getNode()->hasOneUse() &&
7348 Int = DAG.getNode(ISD::AND, SDLoc(N0), IntVT, Int,
7351 return DAG.getNode(ISD::BITCAST, SDLoc(N),
7372 if (N1.getOpcode() == ISD::SETCC &&
7373 TLI.isOperationLegalOrCustom(ISD::BR_CC,
7375 return DAG.getNode(ISD::BR_CC, SDLoc(N), MVT::Other,
7380 if ((N1.hasOneUse() && N1.getOpcode() == ISD::SRL) ||
7381 ((N1.getOpcode() == ISD::TRUNCATE && N1.hasOneUse()) &&
7383 N1.getOperand(0).getOpcode() == ISD::SRL))) {
7385 if (N1.getOpcode() == ISD::TRUNCATE) {
7411 if (Op0.getOpcode() == ISD::AND &&
7412 Op1.getOpcode() == ISD::Constant) {
7415 if (AndOp1.getOpcode() == ISD::Constant) {
7424 ISD::SETNE);
7426 SDValue NewBRCond = DAG.getNode(ISD::BRCOND, SDLoc(N),
7453 if (N1.hasOneUse() && N1.getOpcode() == ISD::XOR) {
7471 return DAG.getNode(ISD::BRCOND, SDLoc(N),
7481 if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) {
7485 Op0.getOpcode() == ISD::XOR) {
7496 Equal ? ISD::SETEQ : ISD::SETNE);
7502 ISD::BRCOND, SDLoc(N),
7529 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC)
7530 return DAG.getNode(ISD::BR_CC, SDLoc(N), MVT::Other,
7557 if (N->getOpcode() == ISD::ADD) {
7565 } else if (N->getOpcode() == ISD::SUB) {
7596 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) &&
7597 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT))
7604 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) &&
7605 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT))
7615 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) ||
7622 ISD::MemIndexedMode AM = ISD::UNINDEXED;
7672 if (Use->getOpcode() != ISD::ADD && Use->getOpcode() != ISD::SUB) {
7775 X0 = (OtherUses[i]->getOpcode() == ISD::SUB && OffsetIdx == 1) ? -1 : 1;
7776 Y0 = (OtherUses[i]->getOpcode() == ISD::SUB && OffsetIdx == 0) ? -1 : 1;
7777 X1 = (AM == ISD::PRE_DEC && !Swapped) ? -1 : 1;
7778 Y1 = (AM == ISD::PRE_DEC && Swapped) ? -1 : 1;
7780 unsigned Opcode = (Y0 * Y1 < 0) ? ISD::SUB : ISD::ADD;
7823 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) &&
7824 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT))
7831 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) &&
7832 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT))
7845 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB))
7850 ISD::MemIndexedMode AM = ISD::UNINDEXED;
7875 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){
7989 if (ISD::isNormalLoad(N) && !LD->isVolatile()) {
7990 if (ISD::isNON_TRUNCStore(Chain.getNode())) {
8030 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
8041 SDValue Token = DAG.getNode(ISD::TokenFactor, SDLoc(N),
8228 if (Origin->getOffset().getOpcode() != ISD::UNDEF)
8239 if (!TLI.isOperationLegal(ISD::LOAD, SliceType))
8253 if (!TLI.isOperationLegal(ISD::ADD, PtrType))
8259 !TLI.isOperationLegal(ISD::ZERO_EXTEND, TruncateType))
8303 BaseAddr = DAG->getNode(ISD::ADD, SDLoc(Origin), ArithType, BaseAddr,
8320 DAG->getNode(ISD::ZERO_EXTEND, SDLoc(LastInst), FinalType, LastInst);
8332 if (Use->getOpcode() != ISD::BITCAST)
8340 if (ArgRC == ResRC || !TLI.isOperationLegal(ISD::LOAD, ResVT))
8360 if (!TLI.isOperationLegal(ISD::LOAD, ResVT))
8519 if (LD->isVolatile() || !ISD::isNormalLoad(LD) ||
8542 if (User->getOpcode() == ISD::SRL && User->hasOneUse() &&
8550 if (User->getOpcode() != ISD::TRUNCATE)
8596 if (SliceInst.getNode()->getOpcode() != ISD::LOAD)
8598 assert(SliceInst->getOpcode() == ISD::LOAD &&
8603 SDValue Chain = DAG.getNode(ISD::TokenFactor, SDLoc(LD), MVT::Other,
8617 if (V->getOpcode() != ISD::AND ||
8619 !ISD::isNormalLoad(V->getOperand(0).getNode()))
8630 else if (Chain->getOpcode() != ISD::TokenFactor)
8711 IVal = DAG.getNode(ISD::SRL, SDLoc(IVal), IVal.getValueType(), IVal,
8726 Ptr = DAG.getNode(ISD::ADD, SDLoc(IVal), Ptr.getValueType(),
8732 IVal = DAG.getNode(ISD::TRUNCATE, SDLoc(IVal), VT, IVal);
8765 if (Opc == ISD::OR) {
8781 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) ||
8782 Value.getOperand(1).getOpcode() != ISD::Constant)
8786 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
8798 if (Opc == ISD::AND)
8823 if (Opc == ISD::AND)
8836 SDValue NewPtr = DAG.getNode(ISD::ADD, SDLoc(LD),
8873 if (ISD::isNormalStore(ST) && ISD::isNormalLoad(Value.getNode()) &&
8887 if (!TLI.isOperationLegal(ISD::LOAD, IntVT) ||
8888 !TLI.isOperationLegal(ISD::STORE, IntVT) ||
8889 !TLI.isDesirableToTransformToIntegerOp(ISD::LOAD, VT) ||
8890 !TLI.isDesirableToTransformToIntegerOp(ISD::STORE, VT))
8958 if (Ptr->getOpcode() != ISD::ADD)
8974 if (Ptr->getOperand(1)->getOpcode() == ISD::MUL)
8982 if (IndexOffset->getOpcode() == ISD::SIGN_EXTEND) {
8988 if (IndexOffset->getOpcode() != ISD::ADD)
8999 if (Index->getOpcode() == ISD::SIGN_EXTEND) {
9043 if (Chain->hasOneUse() && Chain->use_begin()->getOpcode() == ISD::STORE)
9055 if (BasePtr.Base.getOpcode() == ISD::UNDEF)
9339 if (Ld->getExtensionType() != ISD::NON_EXTLOAD)
9399 TLI.isLoadExtLegal(ISD::ZEXTLOAD, StoreTy) &&
9400 TLI.isLoadExtLegal(ISD::SEXTLOAD, StoreTy) &&
9401 TLI.isLoadExtLegal(ISD::EXTLOAD, StoreTy))
9494 if (Value.getOpcode() == ISD::BITCAST && !ST->isTruncatingStore() &&
9502 TLI.isOperationLegalOrCustom(ISD::STORE, SVT)))
9510 if (Value.getOpcode() == ISD::UNDEF && ST->isUnindexed())
9519 if (Value.getOpcode() != ISD::TargetConstantFP) {
9530 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
9540 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) {
9548 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
9566 Ptr = DAG.getNode(ISD::ADD, SDLoc(N), Ptr.getValueType(), Ptr,
9573 return DAG.getNode(ISD::TokenFactor, SDLoc(N), MVT::Other,
9624 SDValue Token = DAG.getNode(ISD::TokenFactor, SDLoc(N),
9679 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE)
9699 } while (ST->getOpcode() != ISD::DELETED_NODE);
9715 if (InVal.getOpcode() == ISD::UNDEF)
9721 if (LegalOperations && !TLI.isOperationLegal(ISD::BUILD_VECTOR, VT))
9736 if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT && InVec.hasOneUse()
9742 SDValue NewOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(N), VT,
9745 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(InVec.getNode()),
9756 if (InVec.getOpcode() == ISD::BUILD_VECTOR && InVec.hasOneUse()) {
9759 } else if (InVec.getOpcode() == ISD::UNDEF) {
9773 DAG.getNode(ISD::ANY_EXTEND, dl, OpVT, InVal) :
9774 DAG.getNode(ISD::TRUNCATE, dl, OpVT, InVal);
9779 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
9790 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VecEltVT))
9808 ISD::MUL, SDLoc(EVE), EltNo.getValueType(), EltNo,
9812 ISD::SUB, SDLoc(EVE), EltNo.getValueType(),
9816 NewPtr = DAG.getNode(ISD::ADD, SDLoc(EVE), PtrType, NewPtr, Offset);
9829 ISD::LoadExtType ExtType = TLI.isLoadExtLegal(ISD::ZEXTLOAD, VecEltVT)
9830 ? ISD::ZEXTLOAD
9831 : ISD::EXTLOAD;
9844 Load = DAG.getNode(ISD::TRUNCATE, SDLoc(EVE), ResultVT, Load);
9846 Load = DAG.getNode(ISD::BITCAST, SDLoc(EVE), ResultVT, Load);
9868 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
9889 if (InVec.getOpcode() == ISD::VECTOR_SHUFFLE
9910 if (SVInVec.getOpcode() == ISD::BUILD_VECTOR) {
9925 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N), NVT,
9939 if (InVec.getOpcode() == ISD::BITCAST) {
9955 ISD::isNormalLoad(InVec.getNode())) {
9975 if (ISD::isNormalLoad(InVec.getNode())) {
9977 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR &&
9979 ISD::isNormalLoad(InVec.getOperand(0).getNode())) {
10004 if (InVec.getOpcode() == ISD::BITCAST) {
10011 if (ISD::isNormalLoad(InVec.getNode())) {
10059 if (In.getOpcode() == ISD::UNDEF) continue;
10061 bool AnyExt = In.getOpcode() == ISD::ANY_EXTEND;
10062 bool ZeroExt = In.getOpcode() == ISD::ZERO_EXTEND;
10112 assert((Cast.getOpcode() == ISD::ANY_EXTEND ||
10113 Cast.getOpcode() == ISD::ZERO_EXTEND ||
10114 Cast.getOpcode() == ISD::UNDEF) && "Invalid cast opcode");
10116 if (Cast.getOpcode() == ISD::UNDEF)
10135 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, Ops);
10140 return DAG.getNode(ISD::BITCAST, dl, VT, BV);
10150 unsigned Opcode = ISD::DELETED_NODE;
10157 if (Opc == ISD::UNDEF)
10161 if (Opcode == ISD::DELETED_NODE &&
10162 (Opc == ISD::UINT_TO_FP || Opc == ISD::SINT_TO_FP)) {
10185 assert((Opcode == ISD::UINT_TO_FP || Opcode == ISD::SINT_TO_FP)
10198 if (In.getOpcode() == ISD::UNDEF)
10203 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, Opnds);
10215 if (ISD::allOperandsUndef(N))
10232 !TLI.isOperationLegalOrCustom(ISD::VECTOR_SHUFFLE, VT))
10238 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
10242 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
10268 if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
10309 VecIn1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
10348 if (ISD::allOperandsUndef(N))
10353 N->getOperand(1)->getOpcode() == ISD::UNDEF) {
10358 if (In->getOpcode() == ISD::BITCAST &&
10372 SDValue Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NVT, Scalar);
10373 return DAG.getNode(ISD::BITCAST, dl, VT, Res);
10380 N->getOperand(0).getOpcode() == ISD::BUILD_VECTOR &&
10381 N->getOperand(1).getOpcode() == ISD::BUILD_VECTOR) {
10400 Opnds.push_back(DAG.getNode(ISD::TRUNCATE, SDLoc(N), MinTy,
10403 Opnds.push_back(DAG.getNode(ISD::TRUNCATE, SDLoc(N), MinTy,
10407 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), VT, Opnds);
10420 if (Op.getOpcode() == ISD::UNDEF)
10424 if (Op.getOpcode() != ISD::EXTRACT_SUBVECTOR)
10462 if (V->getOpcode() == ISD::CONCAT_VECTORS) {
10479 if (V->getOpcode() == ISD::BITCAST)
10482 if (V->getOpcode() == ISD::INSERT_SUBVECTOR) {
10505 return DAG.getNode(ISD::BITCAST, dl, NVT, V->getOperand(1));
10506 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NVT,
10507 DAG.getNode(ISD::BITCAST, dl,
10564 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT, Ops);
10577 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF)
10595 if (N0.getOpcode() == ISD::UNDEF) {
10612 if (N1.getOpcode() == ISD::UNDEF) {
10635 if (V->getOpcode() == ISD::BITCAST) {
10642 if (V->getOpcode() == ISD::BUILD_VECTOR) {
10648 if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
10668 if (N0.getOpcode() == ISD::CONCAT_VECTORS &&
10670 (N1.getOpcode() == ISD::UNDEF ||
10671 (N1.getOpcode() == ISD::CONCAT_VECTORS &&
10681 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG &&
10682 N1.getOpcode() == ISD::UNDEF) {
10704 if (N0.getOperand(1).getOpcode() != ISD::UNDEF) {
10776 if (N0.getOpcode() == ISD::CONCAT_VECTORS &&
10777 N0->getNumOperands() == 2 && N2.getOpcode() == ISD::Constant) {
10784 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT,
10790 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT,
10806 if (N->getOpcode() == ISD::AND) {
10807 if (RHS.getOpcode() == ISD::BITCAST)
10809 if (RHS.getOpcode() == ISD::BUILD_VECTOR) {
10834 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), RVT, ZeroOps);
10835 LHS = DAG.getNode(ISD::BITCAST, dl, RVT, LHS);
10837 return DAG.getNode(ISD::BITCAST, dl, VT, Shuf);
10856 if (LHS.getOpcode() == ISD::BUILD_VECTOR &&
10857 RHS.getOpcode() == ISD::BUILD_VECTOR) {
10869 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV ||
10870 N->getOpcode() == ISD::FDIV) {
10871 if ((RHSOp.getOpcode() == ISD::Constant &&
10873 (RHSOp.getOpcode() == ISD::ConstantFP &&
10886 RHSOp = DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, RHSOp);
10888 LHSOp = DAG.getNode(ISD::TRUNCATE, SDLoc(N), RVT, LHSOp);
10894 if (FoldOp.getOpcode() != ISD::UNDEF &&
10895 FoldOp.getOpcode() != ISD::Constant &&
10896 FoldOp.getOpcode() != ISD::ConstantFP)
10903 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), LHS.getValueType(), Ops);
10911 LHS.getOperand(1).getOpcode() == ISD::UNDEF &&
10912 RHS.getOperand(1).getOpcode() == ISD::UNDEF) {
10937 if (N0.getOpcode() != ISD::BUILD_VECTOR)
10944 if (Op.getOpcode() != ISD::UNDEF &&
10945 Op.getOpcode() != ISD::ConstantFP)
10949 if (FoldOp.getOpcode() != ISD::UNDEF &&
10950 FoldOp.getOpcode() != ISD::ConstantFP)
10959 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), N0.getValueType(), Ops);
10964 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
10975 if (SCC.getOpcode() == ISD::SELECT_CC) {
10976 SDValue SETCC = DAG.getNode(ISD::SETCC, SDLoc(N0),
11012 if (LHS.getOpcode() == ISD::LOAD) {
11025 LLD->getExtensionType() != ISD::EXTLOAD &&
11026 RLD->getExtensionType() != ISD::EXTLOAD) ||
11042 if (TheSelect->getOpcode() == ISD::SELECT) {
11065 Addr = DAG.getNode(ISD::SELECT_CC, SDLoc(TheSelect),
11074 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) {
11082 Load = DAG.getExtLoad(LLD->getExtensionType() == ISD::EXTLOAD ?
11109 ISD::CondCode CC, bool NotExtCompare) {
11136 if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
11137 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
11139 return DAG.getNode(ISD::FABS, DL, VT, N0);
11142 if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
11143 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
11145 return DAG.getNode(ISD::FABS, DL, VT, N3);
11160 (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) !=
11193 CPIdx = DAG.getNode(ISD::ADD, DL, CPIdx.getValueType(), CPIdx,
11205 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT &&
11218 SDValue Shift = DAG.getNode(ISD::SRL, SDLoc(N0),
11223 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
11227 return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
11230 SDValue Shift = DAG.getNode(ISD::SRA, SDLoc(N0),
11237 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
11241 return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
11251 if (CC == ISD::SETEQ && N0->getOpcode() == ISD::AND &&
11263 SDValue Shl = DAG.getNode(ISD::SHL, SDLoc(N0), VT, AndLHS, ShlAmt);
11270 SDValue Shr = DAG.getNode(ISD::SRA, SDLoc(N0), VT, Shl, ShrAmt);
11272 return DAG.getNode(ISD::AND, DL, VT, Shr, N3);
11289 TLI.isOperationLegal(ISD::SETCC,
11300 Temp = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N2),
11304 Temp = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N2),
11316 ISD::SHL, DL, N2.getValueType(), Temp,
11328 TLI.isOperationLegal(ISD::SETCC, getSetCCResultType(XType))) {
11331 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res);
11336 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
11338 TLI.isOperationLegal(ISD::CTLZ, XType))) {
11339 SDValue Ctlz = DAG.getNode(ISD::CTLZ, SDLoc(N0), XType, N0);
11340 return DAG.getNode(ISD::SRL, DL, XType, Ctlz,
11345 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
11346 SDValue NegN0 = DAG.getNode(ISD::SUB, SDLoc(N0),
11349 return DAG.getNode(ISD::SRL, DL, XType,
11350 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0),
11355 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
11356 SDValue Sign = DAG.getNode(ISD::SRL, SDLoc(N0), XType, N0,
11359 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType));
11371 if (((N1C->isNullValue() && (CC == ISD::SETGT || CC == ISD::SETGE)) ||
11372 (N1C->isAllOnesValue() && CC == ISD::SETGT)) &&
11373 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1))
11375 else if (((N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE)) ||
11376 (N1C->isOne() && CC == ISD::SETLT)) &&
11377 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1))
11382 SDValue Shift = DAG.getNode(ISD::SRA, SDLoc(N0), XType,
11386 SDValue Add = DAG.getNode(ISD::ADD, SDLoc(N0),
11390 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift);
11399 SDValue N1, ISD::CondCode Cond,
11406 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
11428 /// BuildUDIV - Given an ISD::UDIV node expressing a divide by constant,
11459 if (Base.getOpcode() == ISD::ADD) {
11619 case ISD::EntryToken:
11623 case ISD::LOAD:
11624 case ISD::STORE: {
11641 case ISD::TokenFactor:
11737 return DAG.getNode(ISD::TokenFactor, SDLoc(N), MVT::Other, Aliases);
